diff mbox series

[v2,3/3] arm64: dts: qcom: sa8295p-adp: Add max20411 on i2c12

Message ID 20230124184440.1421074-4-quic_bjorande@quicinc.com
State New
Headers
Series regulator: Add Maxim MAX20411 support |

Commit Message

Bjorn Andersson Jan. 24, 2023, 6:44 p.m. UTC 
  From: Bjorn Andersson <bjorn.andersson@linaro.org>

The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---

Changes since v1:
- i2c node had changed name

 arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

Comments

Andrew Halaney Jan. 26, 2023, 10:54 p.m. UTC | #1 
On Tue, Jan 24, 2023 at 10:44:40AM -0800, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> 
> The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---
> 
> Changes since v1:
> - i2c node had changed name
> 
>  arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)

I realized today this has to do with the comment over at:

    https://lore.kernel.org/all/30166208-ba9d-e6e6-1cd2-807a80536052@quicinc.com/

and I just didn't realize that the schematic I've started looking at
black boxes the SOM/SIP which holds this... darn I thought I could see
more than I could :(

I took a similiar patch for a spin on sa8540p-ride (which I'll later
submit), and things worked fine (I'm not really consuming the output of
the regulator mind you).

Downstream devicetree indicates all of this looks ok except for possibly
the below comment:

> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> index bb4270e8f551..642000d95812 100644
> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> @@ -266,6 +266,27 @@ &dispcc1 {
>  	status = "okay";
>  };
>  
> +&i2c12 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c12_state>;
> +
> +	status = "okay";
> +
> +	vdd_gfx: regulator@39 {
> +		compatible = "maxim,max20411";
> +		reg = <0x39>;
> +
> +		regulator-name = "vdd_gfx";
> +		regulator-min-microvolt = <800000>;

Is there a reason you chose this instead of the 500000 I see downstream?

> +		regulator-max-microvolt = <968750>;

Likewise, I see in this brief description of the regulator
that the upper bound is higher than this (1.275 V). I am not sure if
the values in the devicetree are supposed to describe the
min/max of the regulator itself, or of what your board can really
handle/needs (the latter I guess makes more sense since you wouldn't want to
accidentally request a current draw that could melt something.. that can
be fun). I do see you've got that min/max in the driver itself (now that
I peaked at that patch).

https://www.analog.com/en/products/MAX20411.html#product-overview

For what it is worth, I also see a SIP document that states vdd_gfx min/max
is 0.56/1.03 V, which is ultimately what you'd feed this into. The
downstream devicetree uses the max value you provide though.

No idea how much faith I should put into the SIP document's bounds, or
downstream, but I thought I should at least highlight them.

Thanks,
Andrew
Konrad Dybcio Jan. 26, 2023, 11:35 p.m. UTC | #2 
On 26.01.2023 23:54, Andrew Halaney wrote:
> On Tue, Jan 24, 2023 at 10:44:40AM -0800, Bjorn Andersson wrote:
>> From: Bjorn Andersson <bjorn.andersson@linaro.org>
>>
>> The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.
>>
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
>> ---
>>
>> Changes since v1:
>> - i2c node had changed name
>>
>>  arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++
>>  1 file changed, 41 insertions(+)
> 
> I realized today this has to do with the comment over at:
> 
>     https://lore.kernel.org/all/30166208-ba9d-e6e6-1cd2-807a80536052@quicinc.com/
> 
> and I just didn't realize that the schematic I've started looking at
> black boxes the SOM/SIP which holds this... darn I thought I could see
> more than I could :(
> 
> I took a similiar patch for a spin on sa8540p-ride (which I'll later
> submit), and things worked fine (I'm not really consuming the output of
> the regulator mind you).
> 
> Downstream devicetree indicates all of this looks ok except for possibly
> the below comment:
> 
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> index bb4270e8f551..642000d95812 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> @@ -266,6 +266,27 @@ &dispcc1 {
>>  	status = "okay";
>>  };
>>  
>> +&i2c12 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&i2c12_state>;
>> +
>> +	status = "okay";
>> +
>> +	vdd_gfx: regulator@39 {
>> +		compatible = "maxim,max20411";
>> +		reg = <0x39>;
>> +
>> +		regulator-name = "vdd_gfx";
>> +		regulator-min-microvolt = <800000>;
> 
> Is there a reason you chose this instead of the 500000 I see downstream?
> 
>> +		regulator-max-microvolt = <968750>;
> 
> Likewise, I see in this brief description of the regulator
> that the upper bound is higher than this (1.275 V). I am not sure if
> the values in the devicetree are supposed to describe the
> min/max of the regulator itself, or of what your board can really
> handle/needs (the latter I guess makes more sense since you wouldn't want to
> accidentally request a current draw that could melt something.. that can
> be fun). I do see you've got that min/max in the driver itself (now that
> I peaked at that patch).
Yes, your suspicions are correct and the DT sets the actual ranges
for the voltage regulators on this specific board while the
hardware reachable ranges are defined in the .c driver.

Konrad
> 
> https://www.analog.com/en/products/MAX20411.html#product-overview
> 
> For what it is worth, I also see a SIP document that states vdd_gfx min/max
> is 0.56/1.03 V, which is ultimately what you'd feed this into. The
> downstream devicetree uses the max value you provide though.
> 
> No idea how much faith I should put into the SIP document's bounds, or
> downstream, but I thought I should at least highlight them.
> 
> Thanks,
> Andrew
>
Andrew Halaney Jan. 26, 2023, 11:43 p.m. UTC | #3 
On Fri, Jan 27, 2023 at 12:35:37AM +0100, Konrad Dybcio wrote:
> 
> 
> On 26.01.2023 23:54, Andrew Halaney wrote:
> > On Tue, Jan 24, 2023 at 10:44:40AM -0800, Bjorn Andersson wrote:
> >> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> >>
> >> The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.
> >>
> >> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> >> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> >> ---
> >>
> >> Changes since v1:
> >> - i2c node had changed name
> >>
> >>  arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++
> >>  1 file changed, 41 insertions(+)
> > 
> > I realized today this has to do with the comment over at:
> > 
> >     https://lore.kernel.org/all/30166208-ba9d-e6e6-1cd2-807a80536052@quicinc.com/
> > 
> > and I just didn't realize that the schematic I've started looking at
> > black boxes the SOM/SIP which holds this... darn I thought I could see
> > more than I could :(
> > 
> > I took a similiar patch for a spin on sa8540p-ride (which I'll later
> > submit), and things worked fine (I'm not really consuming the output of
> > the regulator mind you).
> > 
> > Downstream devicetree indicates all of this looks ok except for possibly
> > the below comment:
> > 
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> >> index bb4270e8f551..642000d95812 100644
> >> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> >> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> >> @@ -266,6 +266,27 @@ &dispcc1 {
> >>  	status = "okay";
> >>  };
> >>  
> >> +&i2c12 {
> >> +	pinctrl-names = "default";
> >> +	pinctrl-0 = <&i2c12_state>;
> >> +
> >> +	status = "okay";
> >> +
> >> +	vdd_gfx: regulator@39 {
> >> +		compatible = "maxim,max20411";
> >> +		reg = <0x39>;
> >> +
> >> +		regulator-name = "vdd_gfx";
> >> +		regulator-min-microvolt = <800000>;
> > 
> > Is there a reason you chose this instead of the 500000 I see downstream?
> > 
> >> +		regulator-max-microvolt = <968750>;
> > 
> > Likewise, I see in this brief description of the regulator
> > that the upper bound is higher than this (1.275 V). I am not sure if
> > the values in the devicetree are supposed to describe the
> > min/max of the regulator itself, or of what your board can really
> > handle/needs (the latter I guess makes more sense since you wouldn't want to
> > accidentally request a current draw that could melt something.. that can
> > be fun). I do see you've got that min/max in the driver itself (now that
> > I peaked at that patch).
> Yes, your suspicions are correct and the DT sets the actual ranges
> for the voltage regulators on this specific board while the
> hardware reachable ranges are defined in the .c driver.
> 
> Konrad

Thanks Konrad, then I think:

Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com>

is appropriate since things are within range on all accounts. I would
appreciate an explanation on the current min/max values though if possible!
Johan Hovold Jan. 27, 2023, 9:55 a.m. UTC | #4 
On Tue, Jan 24, 2023 at 10:44:40AM -0800, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> 
> The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---
> 
> Changes since v1:
> - i2c node had changed name
> 
>  arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> index bb4270e8f551..642000d95812 100644
> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> @@ -266,6 +266,27 @@ &dispcc1 {
>  	status = "okay";
>  };
>  
> +&i2c12 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c12_state>;
> +
> +	status = "okay";
> +
> +	vdd_gfx: regulator@39 {

Nit: Should the label be named 'vreg_gfx' (or 'vreg_vdd_gfx)') for
consistency with rest of the file?

> +		compatible = "maxim,max20411";
> +		reg = <0x39>;
> +
> +		regulator-name = "vdd_gfx";
> +		regulator-min-microvolt = <800000>;
> +		regulator-max-microvolt = <968750>;
> +
> +		enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>;
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vdd_gfx_enable_state>;
> +	};
> +};
> +
>  &mdss0 {
>  	status = "okay";
>  };
> @@ -476,6 +497,10 @@ &pcie4_phy {
>  	status = "okay";
>  };
>  
> +&qup1 {
> +	status = "okay";
> +};
> +
>  &qup2 {
>  	status = "okay";
>  };
> @@ -636,7 +661,23 @@ &xo_board_clk {
>  
>  /* PINCTRL */
>  
> +&pmm8540a_gpios {
> +	vdd_gfx_enable_state: vdd-gfx-enable-state {

For consistency with the rest of sc8280xp, can you rename this

	vdd_gfx_en: vdd-gfx-en-state {

(i.e. drop the 'state' from the label and shorten 'enable')?

> +		pins = "gpio2";
> +		function = "normal";
> +		output-enable;
> +	};
> +};
> +
>  &tlmm {
> +	i2c12_state: i2c12-state {

Similar here, this should be

	i2c12_default: i2c12-default-state {

> +		pins = "gpio0", "gpio1";
> +		function = "qup12";
> +

And this newline can be removed.

> +		drive-strength = <2>;
> +		bias-pull-up;
> +	};
> +
>  	pcie2a_default: pcie2a-default-state {
>  		clkreq-n-pins {
>  			pins = "gpio142";

Johan
Bjorn Andersson Jan. 30, 2023, 3:56 a.m. UTC | #5 
On Fri, Jan 27, 2023 at 10:55:21AM +0100, Johan Hovold wrote:
> On Tue, Jan 24, 2023 at 10:44:40AM -0800, Bjorn Andersson wrote:
> > From: Bjorn Andersson <bjorn.andersson@linaro.org>
> > 
> > The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> > ---
> > 
> > Changes since v1:
> > - i2c node had changed name
> > 
> >  arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > index bb4270e8f551..642000d95812 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > @@ -266,6 +266,27 @@ &dispcc1 {
> >  	status = "okay";
> >  };
> >  
> > +&i2c12 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c12_state>;
> > +
> > +	status = "okay";
> > +
> > +	vdd_gfx: regulator@39 {
> 
> Nit: Should the label be named 'vreg_gfx' (or 'vreg_vdd_gfx)') for
> consistency with rest of the file?
> 

I will investigate what the appropriate name is, consistency would be
nice though.

> > +		compatible = "maxim,max20411";
> > +		reg = <0x39>;
> > +
> > +		regulator-name = "vdd_gfx";
> > +		regulator-min-microvolt = <800000>;
> > +		regulator-max-microvolt = <968750>;
> > +
> > +		enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>;
> > +
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&vdd_gfx_enable_state>;
> > +	};
> > +};
> > +
> >  &mdss0 {
> >  	status = "okay";
> >  };
> > @@ -476,6 +497,10 @@ &pcie4_phy {
> >  	status = "okay";
> >  };
> >  
> > +&qup1 {
> > +	status = "okay";
> > +};
> > +
> >  &qup2 {
> >  	status = "okay";
> >  };
> > @@ -636,7 +661,23 @@ &xo_board_clk {
> >  
> >  /* PINCTRL */
> >  
> > +&pmm8540a_gpios {
> > +	vdd_gfx_enable_state: vdd-gfx-enable-state {
> 
> For consistency with the rest of sc8280xp, can you rename this
> 
> 	vdd_gfx_en: vdd-gfx-en-state {
> 
> (i.e. drop the 'state' from the label and shorten 'enable')?
> 

Will do.

> > +		pins = "gpio2";
> > +		function = "normal";
> > +		output-enable;
> > +	};
> > +};
> > +
> >  &tlmm {
> > +	i2c12_state: i2c12-state {
> 
> Similar here, this should be
> 
> 	i2c12_default: i2c12-default-state {
> 

Sounds reasonable.

> > +		pins = "gpio0", "gpio1";
> > +		function = "qup12";
> > +
> 
> And this newline can be removed.
> 

Sure

> > +		drive-strength = <2>;
> > +		bias-pull-up;
> > +	};
> > +
> >  	pcie2a_default: pcie2a-default-state {
> >  		clkreq-n-pins {
> >  			pins = "gpio142";
> 
> Johan

Thanks Johan,
Bjorn
Bjorn Andersson Jan. 30, 2023, 3:57 a.m. UTC | #6 
On Thu, Jan 26, 2023 at 05:43:54PM -0600, Andrew Halaney wrote:
> On Fri, Jan 27, 2023 at 12:35:37AM +0100, Konrad Dybcio wrote:
> > 
> > 
> > On 26.01.2023 23:54, Andrew Halaney wrote:
> > > On Tue, Jan 24, 2023 at 10:44:40AM -0800, Bjorn Andersson wrote:
> > >> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> > >>
> > >> The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.
> > >>
> > >> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > >> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> > >> ---
> > >>
> > >> Changes since v1:
> > >> - i2c node had changed name
> > >>
> > >>  arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++
> > >>  1 file changed, 41 insertions(+)
> > > 
> > > I realized today this has to do with the comment over at:
> > > 
> > >     https://lore.kernel.org/all/30166208-ba9d-e6e6-1cd2-807a80536052@quicinc.com/
> > > 
> > > and I just didn't realize that the schematic I've started looking at
> > > black boxes the SOM/SIP which holds this... darn I thought I could see
> > > more than I could :(
> > > 
> > > I took a similiar patch for a spin on sa8540p-ride (which I'll later
> > > submit), and things worked fine (I'm not really consuming the output of
> > > the regulator mind you).
> > > 
> > > Downstream devicetree indicates all of this looks ok except for possibly
> > > the below comment:
> > > 
> > >>
> > >> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > >> index bb4270e8f551..642000d95812 100644
> > >> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > >> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > >> @@ -266,6 +266,27 @@ &dispcc1 {
> > >>  	status = "okay";
> > >>  };
> > >>  
> > >> +&i2c12 {
> > >> +	pinctrl-names = "default";
> > >> +	pinctrl-0 = <&i2c12_state>;
> > >> +
> > >> +	status = "okay";
> > >> +
> > >> +	vdd_gfx: regulator@39 {
> > >> +		compatible = "maxim,max20411";
> > >> +		reg = <0x39>;
> > >> +
> > >> +		regulator-name = "vdd_gfx";
> > >> +		regulator-min-microvolt = <800000>;
> > > 
> > > Is there a reason you chose this instead of the 500000 I see downstream?
> > > 
> > >> +		regulator-max-microvolt = <968750>;
> > > 
> > > Likewise, I see in this brief description of the regulator
> > > that the upper bound is higher than this (1.275 V). I am not sure if
> > > the values in the devicetree are supposed to describe the
> > > min/max of the regulator itself, or of what your board can really
> > > handle/needs (the latter I guess makes more sense since you wouldn't want to
> > > accidentally request a current draw that could melt something.. that can
> > > be fun). I do see you've got that min/max in the driver itself (now that
> > > I peaked at that patch).
> > Yes, your suspicions are correct and the DT sets the actual ranges
> > for the voltage regulators on this specific board while the
> > hardware reachable ranges are defined in the .c driver.
> > 
> > Konrad
> 
> Thanks Konrad, then I think:
> 
> Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
> Tested-by: Andrew Halaney <ahalaney@redhat.com>
> 
> is appropriate since things are within range on all accounts. I would
> appreciate an explanation on the current min/max values though if possible!
> 

I will add a line about the range as I resubmit the patch.

Thanks,
Bjorn
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index bb4270e8f551..642000d95812 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -266,6 +266,27 @@  &dispcc1 {
 	status = "okay";
 };
 
+&i2c12 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c12_state>;
+
+	status = "okay";
+
+	vdd_gfx: regulator@39 {
+		compatible = "maxim,max20411";
+		reg = <0x39>;
+
+		regulator-name = "vdd_gfx";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <968750>;
+
+		enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vdd_gfx_enable_state>;
+	};
+};
+
 &mdss0 {
 	status = "okay";
 };
@@ -476,6 +497,10 @@  &pcie4_phy {
 	status = "okay";
 };
 
+&qup1 {
+	status = "okay";
+};
+
 &qup2 {
 	status = "okay";
 };
@@ -636,7 +661,23 @@  &xo_board_clk {
 
 /* PINCTRL */
 
+&pmm8540a_gpios {
+	vdd_gfx_enable_state: vdd-gfx-enable-state {
+		pins = "gpio2";
+		function = "normal";
+		output-enable;
+	};
+};
+
 &tlmm {
+	i2c12_state: i2c12-state {
+		pins = "gpio0", "gpio1";
+		function = "qup12";
+
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
 	pcie2a_default: pcie2a-default-state {
 		clkreq-n-pins {
 			pins = "gpio142";