[v6,1/6] arm64: dts: Add i.MX8MM PCIe EP support
Commit Message
Add i.MX8MM PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++
1 file changed, 24 insertions(+)
Comments
On 20/01/2023 06:25, Richard Zhu wrote:
> Add i.MX8MM PCIe EP support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 31f4548f85cf..9662aeccdb3b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 {
> status = "disabled";
> };
>
> + pcie0_ep: pcie_ep@33800000 {
No underscores in node names.
> + compatible = "fsl,imx8mm-pcie-ep";
Did you test it with bindings? Does it pass without warnings?
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 2023年1月20日 16:08
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; shawnguo@kernel.org; Peng Fan
> <peng.fan@nxp.com>; marex@denx.de; Marcel Ziswiler
> <marcel.ziswiler@toradex.com>; tharvey@gateworks.com; Frank Li
> <frank.li@nxp.com>
> Cc: lorenzo.pieralisi@arm.com; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v6 1/6] arm64: dts: Add i.MX8MM PCIe EP support
>
> On 20/01/2023 06:25, Richard Zhu wrote:
> > Add i.MX8MM PCIe EP support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24
> +++++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index 31f4548f85cf..9662aeccdb3b 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 {
> > status = "disabled";
> > };
> >
> > + pcie0_ep: pcie_ep@33800000 {
>
> No underscores in node names.
Hi Krzystof:
Thanks for your review comments.
Sorry to reply late, since I'm taking the Spring Festival Vacation in the past days.
Got that. Would be changed later.
>
> > + compatible = "fsl,imx8mm-pcie-ep";
>
> Did you test it with bindings? Does it pass without warnings?
>
>
It's my fault that I'm trying to let fsl,imx6q-pcie.yaml to cover the binding
DT-schema for the Endpoint modes.
One standalone fsl,imx6q-pcie-ep.yaml should be created as DT-schema for i.MX
PCIe Endpoint modes.
I would summit next version a moment later. Please help to review them.
Thanks in advanced.
Best Regards
Richard Zhu
> Best regards,
> Krzysztof
@@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 {
status = "disabled";
};
+ pcie0_ep: pcie_ep@33800000 {
+ compatible = "fsl,imx8mm-pcie-ep";
+ reg = <0x33800000 0x400000>,
+ <0x18000000 0x8000000>;
+ reg-names = "regs", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ fsl,max-link-speed = <2>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;