Change AVX512FP16 to AVX512-FP16 in the document.

Message ID 20230129012041.930809-1-hongtao.liu@intel.com
State Accepted
Headers
Series Change AVX512FP16 to AVX512-FP16 in the document. |

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Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

liuhongt Jan. 29, 2023, 1:20 a.m. UTC
  The official name is AVX512-FP16.

Ready to push to trunk.

gcc/ChangeLog:

	* config/i386/i386.opt: Change AVX512FP16 to AVX512-FP16.
	* doc/invoke.texi: Ditto.
---
 gcc/config/i386/i386.opt | 2 +-
 gcc/doc/invoke.texi      | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)
  

Comments

Gerald Pfeifer Jan. 29, 2023, 9:55 a.m. UTC | #1
On Sun, 29 Jan 2023, liuhongt wrote:
> The official name is AVX512-FP16.
> 
> Ready to push to trunk.
> 
> gcc/ChangeLog:
> 
> 	* config/i386/i386.opt: Change AVX512FP16 to AVX512-FP16.
> 	* doc/invoke.texi: Ditto.

Ok, thank you.

(And okay to backport to older branches as/if you want.)

Gerald
  

Patch

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index feeb7dee9cc..7d57f617d65 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1209,7 +1209,7 @@  Support MWAIT and MONITOR built-in functions and code generation.
 
 mavx512fp16
 Target Mask(ISA2_AVX512FP16) Var(ix86_isa_flags2) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512FP16 built-in functions and code generation.
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512-FP16 built-in functions and code generation.
 
 mdirect-extern-access
 Target Var(ix86_direct_extern_access) Init(1)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a371cd91ef8..3d059467690 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -32336,7 +32336,7 @@  AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,
 AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,
 VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB,
 MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK,
-UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16 and AVX512BF16
+UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512-FP16 and AVX512BF16
 instruction set support.
 
 @item alderlake
@@ -32363,7 +32363,7 @@  AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,
 AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,
 VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB,
 MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
-SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16,
+SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512-FP16,
 AVX512BF16, AMX-FP16 and PREFETCHI instruction set support.
 
 @item k6
@@ -33229,7 +33229,7 @@  WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,
 XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
 GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
 ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
-UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512FP16,
+UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
 AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT or
 CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-}
 option to disable use of these instructions.