[v4,03/11] arm: dts: qcom: mdm9615: add missing reg in cpu@0 node

Message ID 20220928-mdm9615-dt-schema-fixes-v4-3-dac2dfaac703@linaro.org
State New
Headers
Series arm: qcom: mdm9615: first round of bindings and DT fixes |

Commit Message

Neil Armstrong Oct. 21, 2022, 9:06 a.m. UTC
  Fixes cpu@0: 'reg' is a required property from dtbs check.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
 1 file changed, 1 insertion(+)
  

Comments

Konrad Dybcio Oct. 21, 2022, 9:14 a.m. UTC | #1
On 21.10.2022 11:06, Neil Armstrong wrote:
> Fixes cpu@0: 'reg' is a required property from dtbs check.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad
>  arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> index de36e4545e75..eaa3236f62db 100644
> --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
> +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> @@ -27,6 +27,7 @@ cpus {
>  
>  		cpu0: cpu@0 {
>  			compatible = "arm,cortex-a5";
> +			reg = <0>;
>  			device_type = "cpu";
>  			next-level-cache = <&L2>;
>  		};
>
  

Patch

diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index de36e4545e75..eaa3236f62db 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -27,6 +27,7 @@  cpus {
 
 		cpu0: cpu@0 {
 			compatible = "arm,cortex-a5";
+			reg = <0>;
 			device_type = "cpu";
 			next-level-cache = <&L2>;
 		};