diff mbox series

RISC-V: Add type attribute for atomic instructions.

Message ID 20221021050159.121335-1-monk.chiang@sifive.com
State Unresolved
Headers
Series RISC-V: Add type attribute for atomic instructions. |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Monk Chiang Oct. 21, 2022, 5:01 a.m. UTC 
  gcc/ChangeLog:

	* config/riscv/riscv.md: Add atomic type attribute.
	* config/riscv/sync.md: Add atomic type for atomic instructions.
---
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/sync.md  | 15 ++++++++++-----
 2 files changed, 11 insertions(+), 6 deletions(-)

Comments

Kito Cheng Oct. 21, 2022, 7:35 a.m. UTC | #1 
Committed, thanks :)

On Fri, Oct 21, 2022 at 1:02 PM Monk Chiang <monk.chiang@sifive.com> wrote:
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Add atomic type attribute.
>         * config/riscv/sync.md: Add atomic type for atomic instructions.
> ---
>  gcc/config/riscv/riscv.md |  2 +-
>  gcc/config/riscv/sync.md  | 15 ++++++++++-----
>  2 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index b3654915fde..9384ced0447 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -317,7 +317,7 @@
>    "unknown,branch,jump,call,load,fpload,store,fpstore,
>     mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
>     fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
> -   rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
> +   atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
>     vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>     vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
>     vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
> index 7deb290d9dc..449f275e6a2 100644
> --- a/gcc/config/riscv/sync.md
> +++ b/gcc/config/riscv/sync.md
> @@ -62,7 +62,8 @@
>        UNSPEC_ATOMIC_STORE))]
>    "TARGET_ATOMIC"
>    "%F2amoswap.<amo>%A2 zero,%z1,%0"
> -  [(set (attr "length") (const_int 8))])
> +  [(set_attr "type" "atomic")
> +   (set (attr "length") (const_int 8))])
>
>  (define_insn "atomic_<atomic_optab><mode>"
>    [(set (match_operand:GPR 0 "memory_operand" "+A")
> @@ -73,7 +74,8 @@
>          UNSPEC_SYNC_OLD_OP))]
>    "TARGET_ATOMIC"
>    "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
> -  [(set (attr "length") (const_int 8))])
> +  [(set_attr "type" "atomic")
> +   (set (attr "length") (const_int 8))])
>
>  (define_insn "atomic_fetch_<atomic_optab><mode>"
>    [(set (match_operand:GPR 0 "register_operand" "=&r")
> @@ -86,7 +88,8 @@
>          UNSPEC_SYNC_OLD_OP))]
>    "TARGET_ATOMIC"
>    "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
> -  [(set (attr "length") (const_int 8))])
> +  [(set_attr "type" "atomic")
> +   (set (attr "length") (const_int 8))])
>
>  (define_insn "atomic_exchange<mode>"
>    [(set (match_operand:GPR 0 "register_operand" "=&r")
> @@ -98,7 +101,8 @@
>         (match_operand:GPR 2 "register_operand" "0"))]
>    "TARGET_ATOMIC"
>    "%F3amoswap.<amo>%A3 %0,%z2,%1"
> -  [(set (attr "length") (const_int 8))])
> +  [(set_attr "type" "atomic")
> +   (set (attr "length") (const_int 8))])
>
>  (define_insn "atomic_cas_value_strong<mode>"
>    [(set (match_operand:GPR 0 "register_operand" "=&r")
> @@ -112,7 +116,8 @@
>     (clobber (match_scratch:GPR 6 "=&r"))]
>    "TARGET_ATOMIC"
>    "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
> -  [(set (attr "length") (const_int 20))])
> +  [(set_attr "type" "atomic")
> +   (set (attr "length") (const_int 20))])
>
>  (define_expand "atomic_compare_and_swap<mode>"
>    [(match_operand:SI 0 "register_operand" "")   ;; bool output
> --
> 2.37.2
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b3654915fde..9384ced0447 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -317,7 +317,7 @@ 
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
-   rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
    vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 7deb290d9dc..449f275e6a2 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -62,7 +62,8 @@ 
       UNSPEC_ATOMIC_STORE))]
   "TARGET_ATOMIC"
   "%F2amoswap.<amo>%A2 zero,%z1,%0"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "atomic_<atomic_optab><mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+A")
@@ -73,7 +74,8 @@ 
 	 UNSPEC_SYNC_OLD_OP))]
   "TARGET_ATOMIC"
   "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "atomic_fetch_<atomic_optab><mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -86,7 +88,8 @@ 
 	 UNSPEC_SYNC_OLD_OP))]
   "TARGET_ATOMIC"
   "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "atomic_exchange<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -98,7 +101,8 @@ 
 	(match_operand:GPR 2 "register_operand" "0"))]
   "TARGET_ATOMIC"
   "%F3amoswap.<amo>%A3 %0,%z2,%1"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "atomic_cas_value_strong<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -112,7 +116,8 @@ 
    (clobber (match_scratch:GPR 6 "=&r"))]
   "TARGET_ATOMIC"
   "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
-  [(set (attr "length") (const_int 20))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 20))])
 
 (define_expand "atomic_compare_and_swap<mode>"
   [(match_operand:SI 0 "register_operand" "")   ;; bool output