Message ID | 20221019170657.68014-2-dinguyen@kernel.org |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp441112wrs; Wed, 19 Oct 2022 10:14:20 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5thWfkmtJqijtZgZuel0Vbi7/2qbGzuK77bWzVZknPwwuyhPjvLadY9lRRgYwYtH7jlT+G X-Received: by 2002:a17:90a:b118:b0:20d:65f4:fde9 with SMTP id z24-20020a17090ab11800b0020d65f4fde9mr44768846pjq.184.1666199649937; Wed, 19 Oct 2022 10:14:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666199649; cv=none; d=google.com; s=arc-20160816; b=Osauq6lnoxYtbPO8jdhoEUredFN0b6DnRfUp3y6brzOlkaYJasIaPd+S7UbOmfD/GW IotgTmWZsRgSYzQLxmlYmOZBZ2FBcMBFYv5E9gAhncrpCS4dEuyVoCnY7c5Py1E1B3il DX81heDABsiuNcu/brn4Q9UoZ6hXcPyp4Ifa34ia+a3FMe8Z+0LLuARElg0P63Vxy+Cn eA6e7qC/iDlnkIEQFURv8sAvAuO2d93G6aaocCVphVLWHcXCGHZXIaZx2I8g0qMraMCv t4RHZ0kUJLH9Z3K2U576aBtkLutJ6CczGuaOrLXD4/+1yWhO4muiR0eFLyuWh902qjqu xTbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HB56lgWxOFD+dVrosqnYTIwEIgr+1z8cJQuKzsAZp1k=; b=L2HJdzx887LXDCJUzvrecVVOby0Rzy52pPTk/6qnLkSJNRXqxrhw8Z8VBOiR3PEXyR uopr08A0f4Gf8pVeUqKuWC7HGdQvMjBXEzn9daY2GEjCJIQpo+5boSHssE4FdMYzwHUw b3v3YhAK9VYZKYMjHHnCvwoqlzu2DV8sQ6594VeTroQtHeF8ycjnR55pAjSl+pJc+FfA HRYQeiGhQA93Jx75srrqRvlCdct3tSd+Wnp19UBfMilDs0PeosTWCH4zHk+SOfA2IKS8 mPucVdVwV1nxYxpUJxGxxKeIqmd46BqGgTXw88Aa3FtC1fH8c8FznEzd+LzoAjQFk9mc h2ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=duAoc9H9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w184-20020a6282c1000000b00562e2899394si17080164pfd.310.2022.10.19.10.13.56; Wed, 19 Oct 2022 10:14:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=duAoc9H9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231536AbiJSRHr (ORCPT <rfc822;samuel.l.nystrom@gmail.com> + 99 others); Wed, 19 Oct 2022 13:07:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230469AbiJSRHj (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 19 Oct 2022 13:07:39 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31DBF1BFBB7; Wed, 19 Oct 2022 10:07:39 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D5737B82566; Wed, 19 Oct 2022 17:07:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 785C8C433D7; Wed, 19 Oct 2022 17:07:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666199256; bh=Dk8qulf7jy4RWXliAjjhHRDUCVMa6Eye2Ux3gVAfoAY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=duAoc9H9OeX3W/6PGFEYsZT011cxJEKkxYnu1SMaRL3cH07K3KMnNZF0Z1+dokqeN EhBe0DTaRGyqE9oIJE82E4KnIWnhRlwwe0Gif6yOoyqTvRdrLjn6vRyXApie32+DgZ BkpPsjhJWb+iQ0ZhyZ5dYhE8EpYHDr6D+U4kHa+344RyxDeyy636ZRQgyLIzNQKFkv ugQppV8t6Uv5xKxqWX8E0cs/YcwMacVgCB2644k1YHsoYj7X/jX/nt2QWbk20kbKTO 6F1AyUCQVZomcwATxgMRj4I9WdxF4Dh4vEVYoNYSuAtedpk64cnEFdz228x3U8LXAC r7BUVzkBJyx3Q== From: Dinh Nguyen <dinguyen@kernel.org> To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv5 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Date: Wed, 19 Oct 2022 12:06:52 -0500 Message-Id: <20221019170657.68014-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019170657.68014-1-dinguyen@kernel.org> References: <20221019170657.68014-1-dinguyen@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747136964512184627?= X-GMAIL-MSGID: =?utf-8?q?1747136964512184627?= |
Series |
arm: socfpga: use clk-phase-sd-hs
|
|
Commit Message
Dinh Nguyen
Oct. 19, 2022, 5:06 p.m. UTC
Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v5: document reg shift
v4: add else statement
v3: document that the "altr,sysmgr-syscon" binding is only applicable to
"altr,socfpga-dw-mshc"
v2: document "altr,sysmgr-syscon" in the MMC section
---
.../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++--
1 file changed, 29 insertions(+), 3 deletions(-)
Comments
On Wed, 19 Oct 2022 12:06:52 -0500, Dinh Nguyen wrote: > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > v5: document reg shift > v4: add else statement > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > "altr,socfpga-dw-mshc" > v2: document "altr,sysmgr-syscon" in the MMC section > --- > .../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++-- > 1 file changed, 29 insertions(+), 3 deletions(-) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb arch/arm/boot/dts/socfpga_vt.dtb dwmmc0@ff704000: 'altr,sysmgr-syscon' is a required property arch/arm/boot/dts/socfpga_arria5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'cd-gpios', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) arch/arm/boot/dts/socfpga_arria5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb arch/arm/boot/dts/socfpga_vt.dtb dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb dwmmc0@ff808000: 'altr,sysmgr-syscon' is a required property arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb mmc@ff808000: 'altr,sysmgr-syscon' is a required property arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb mmc@ff808000: Unevaluated properties are not allowed ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing', 'iommus' were unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb mmc@ff808000: Unevaluated properties are not allowed ('iommus' was unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dtb arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dtb arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb mmcsd@40004000: $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: clock-names:0: 'biu' was expected arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: clock-names:1: 'ciu' was expected arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: Unevaluated properties are not allowed ('bus-width', 'clock-names', 'resets', 'vmmc-supply' were unexpected) arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: Unevaluated properties are not allowed ('clock-names', 'resets' were unexpected) arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb
On 19/10/2022 13:06, Dinh Nguyen wrote: Thank you for your patch. There is something to discuss/improve. > -allOf: > - - $ref: "synopsys-dw-mshc-common.yaml#" > - > maintainers: > - Ulf Hansson <ulf.hansson@linaro.org> > > @@ -38,6 +35,35 @@ properties: > - const: biu > - const: ciu > > + altr,sysmgr-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to the sysmgr node > + - description: register offset that controls the SDMMC clock phase > + - description: register shift for the smplsel(drive in) setting > + description: > + Contains the phandle to System Manager block that contains > + the SDMMC clock-phase control register. The first value is the pointer > + to the sysmgr, the 2nd value is the register offset for the SDMMC > + clock phase register, and the 3rd value is the bit shift for the > + smplsel(drive in) setting. > + > +allOf: > + - $ref: "synopsys-dw-mshc-common.yaml#" If there is going to be resend, please drop quotes here. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Wed, Oct 19, 2022 at 06:31:53PM -0500, Rob Herring wrote: > On Wed, 19 Oct 2022 12:06:52 -0500, Dinh Nguyen wrote: > > Document the optional "altr,sysmgr-syscon" binding that is used to > > access the System Manager register that controls the SDMMC clock > > phase. > > > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > > --- > > v5: document reg shift > > v4: add else statement > > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > > "altr,socfpga-dw-mshc" > > v2: document "altr,sysmgr-syscon" in the MMC section > > --- > > .../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++-- > > 1 file changed, 29 insertions(+), 3 deletions(-) > > > > Running 'make dtbs_check' with the schema in this patch gives the > following warnings. Consider if they are expected or the schema is > incorrect. These may not be new warnings. > > Note that it is not yet a requirement to have 0 warnings for dtbs_check. > This will change in the future. > > Full log is available here: https://patchwork.ozlabs.org/patch/ > > > dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' Not necessary for this series, but it would be nice if existing warnings were fixed before adding new things. Especially since most of the warnings on this common bindings are all socfpga. It may become required at some point, not just nice. The node name is the cause of most/all the unevaluated property warnings. > arch/arm/boot/dts/socfpga_arria5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb > arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb > arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb > arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb > arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb > arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb > arch/arm/boot/dts/socfpga_vt.dtb > > dwmmc0@ff704000: 'altr,sysmgr-syscon' is a required property > arch/arm/boot/dts/socfpga_arria5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb > arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb > arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb > arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb > arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb > arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb I thought it was optional? New required properties are a possible ABI break. Rob
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..950fa6bd11fd 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson <ulf.hansson@linaro.org> @@ -38,6 +35,35 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + Contains the phandle to System Manager block that contains + the SDMMC clock-phase control register. The first value is the pointer + to the sysmgr, the 2nd value is the register offset for the SDMMC + clock phase register, and the 3rd value is the bit shift for the + smplsel(drive in) setting. + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + required: + - altr,sysmgr-syscon + else: + properties: + altr,sysmgr-syscon: false + required: - compatible - reg