diff mbox series

[PATCHv5,1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"

Message ID 20221019170657.68014-2-dinguyen@kernel.org
State New
Headers
Series arm: socfpga: use clk-phase-sd-hs |

Commit Message

Dinh Nguyen Oct. 19, 2022, 5:06 p.m. UTC 
  Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v5: document reg shift
v4: add else statement
v3: document that the "altr,sysmgr-syscon" binding is only applicable to
    "altr,socfpga-dw-mshc"
v2: document "altr,sysmgr-syscon" in the MMC section
---
 .../bindings/mmc/synopsys-dw-mshc.yaml        | 32 +++++++++++++++++--
 1 file changed, 29 insertions(+), 3 deletions(-)

Comments

Rob Herring Oct. 19, 2022, 11:31 p.m. UTC | #1 
On Wed, 19 Oct 2022 12:06:52 -0500, Dinh Nguyen wrote:
> Document the optional "altr,sysmgr-syscon" binding that is used to
> access the System Manager register that controls the SDMMC clock
> phase.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v5: document reg shift
> v4: add else statement
> v3: document that the "altr,sysmgr-syscon" binding is only applicable to
>     "altr,socfpga-dw-mshc"
> v2: document "altr,sysmgr-syscon" in the MMC section
> ---
>  .../bindings/mmc/synopsys-dw-mshc.yaml        | 32 +++++++++++++++++--
>  1 file changed, 29 insertions(+), 3 deletions(-)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/


dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$'
	arch/arm/boot/dts/socfpga_arria5_socdk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb
	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb
	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb
	arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb
	arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb
	arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb
	arch/arm/boot/dts/socfpga_vt.dtb

dwmmc0@ff704000: 'altr,sysmgr-syscon' is a required property
	arch/arm/boot/dts/socfpga_arria5_socdk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb
	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb
	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb
	arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb
	arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb

dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'cd-gpios', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected)
	arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb

dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected)
	arch/arm/boot/dts/socfpga_arria5_socdk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb
	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb
	arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb

dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected)
	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb
	arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb
	arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb
	arch/arm/boot/dts/socfpga_vt.dtb

dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$'
	arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb
	arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb
	arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb
	arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb

dwmmc0@ff808000: 'altr,sysmgr-syscon' is a required property
	arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb
	arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb

dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected)
	arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb

dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected)
	arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb

dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'fifo-depth', 'resets' were unexpected)
	arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb
	arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb

mmc@ff808000: 'altr,sysmgr-syscon' is a required property
	arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb
	arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb
	arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb
	arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb

mmc@ff808000: Unevaluated properties are not allowed ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing', 'iommus' were unexpected)
	arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb

mmc@ff808000: Unevaluated properties are not allowed ('iommus' was unexpected)
	arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb
	arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb
	arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dtb
	arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb
	arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dtb
	arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb

mmcsd@40004000: $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$'
	arch/arm/boot/dts/lpc4337-ciaa.dtb
	arch/arm/boot/dts/lpc4350-hitex-eval.dtb
	arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb
	arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb

mmcsd@40004000: clock-names:0: 'biu' was expected
	arch/arm/boot/dts/lpc4337-ciaa.dtb
	arch/arm/boot/dts/lpc4350-hitex-eval.dtb
	arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb
	arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb

mmcsd@40004000: clock-names:1: 'ciu' was expected
	arch/arm/boot/dts/lpc4337-ciaa.dtb
	arch/arm/boot/dts/lpc4350-hitex-eval.dtb
	arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb
	arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb

mmcsd@40004000: Unevaluated properties are not allowed ('bus-width', 'clock-names', 'resets', 'vmmc-supply' were unexpected)
	arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb
	arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb

mmcsd@40004000: Unevaluated properties are not allowed ('clock-names', 'resets' were unexpected)
	arch/arm/boot/dts/lpc4337-ciaa.dtb
	arch/arm/boot/dts/lpc4350-hitex-eval.dtb
Krzysztof Kozlowski Oct. 20, 2022, 6:20 p.m. UTC | #2 
On 19/10/2022 13:06, Dinh Nguyen wrote:

Thank you for your patch. There is something to discuss/improve.

> -allOf:
> -  - $ref: "synopsys-dw-mshc-common.yaml#"
> -
>  maintainers:
>    - Ulf Hansson <ulf.hansson@linaro.org>
>  
> @@ -38,6 +35,35 @@ properties:
>        - const: biu
>        - const: ciu
>  
> +  altr,sysmgr-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to the sysmgr node
> +          - description: register offset that controls the SDMMC clock phase
> +          - description: register shift for the smplsel(drive in) setting
> +    description:
> +      Contains the phandle to System Manager block that contains
> +      the SDMMC clock-phase control register. The first value is the pointer
> +      to the sysmgr, the 2nd value is the register offset for the SDMMC
> +      clock phase register, and the 3rd value is the bit shift for the
> +      smplsel(drive in) setting.
> +
> +allOf:
> +  - $ref: "synopsys-dw-mshc-common.yaml#"

If there is going to be resend, please drop quotes here.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Rob Herring Oct. 20, 2022, 11:01 p.m. UTC | #3 
On Wed, Oct 19, 2022 at 06:31:53PM -0500, Rob Herring wrote:
> On Wed, 19 Oct 2022 12:06:52 -0500, Dinh Nguyen wrote:
> > Document the optional "altr,sysmgr-syscon" binding that is used to
> > access the System Manager register that controls the SDMMC clock
> > phase.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> > ---
> > v5: document reg shift
> > v4: add else statement
> > v3: document that the "altr,sysmgr-syscon" binding is only applicable to
> >     "altr,socfpga-dw-mshc"
> > v2: document "altr,sysmgr-syscon" in the MMC section
> > ---
> >  .../bindings/mmc/synopsys-dw-mshc.yaml        | 32 +++++++++++++++++--
> >  1 file changed, 29 insertions(+), 3 deletions(-)
> > 
> 
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
> 
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
> 
> Full log is available here: https://patchwork.ozlabs.org/patch/
> 
> 
> dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$'

Not necessary for this series, but it would be nice if existing warnings 
were fixed before adding new things. Especially since most of the  
warnings on this common bindings are all socfpga. It may become 
required at some point, not just nice.

The node name is the cause of most/all the unevaluated property 
warnings.

> 	arch/arm/boot/dts/socfpga_arria5_socdk.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb
> 	arch/arm/boot/dts/socfpga_vt.dtb
> 
> dwmmc0@ff704000: 'altr,sysmgr-syscon' is a required property
> 	arch/arm/boot/dts/socfpga_arria5_socdk.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb
> 	arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb

I thought it was optional? New required properties are a possible ABI 
break.

Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
index ae6d6fca79e2..950fa6bd11fd 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
@@ -6,9 +6,6 @@  $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Synopsys Designware Mobile Storage Host Controller Binding
 
-allOf:
-  - $ref: "synopsys-dw-mshc-common.yaml#"
-
 maintainers:
   - Ulf Hansson <ulf.hansson@linaro.org>
 
@@ -38,6 +35,35 @@  properties:
       - const: biu
       - const: ciu
 
+  altr,sysmgr-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to the sysmgr node
+          - description: register offset that controls the SDMMC clock phase
+          - description: register shift for the smplsel(drive in) setting
+    description:
+      Contains the phandle to System Manager block that contains
+      the SDMMC clock-phase control register. The first value is the pointer
+      to the sysmgr, the 2nd value is the register offset for the SDMMC
+      clock phase register, and the 3rd value is the bit shift for the
+      smplsel(drive in) setting.
+
+allOf:
+  - $ref: "synopsys-dw-mshc-common.yaml#"
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,socfpga-dw-mshc
+    then:
+      required:
+        - altr,sysmgr-syscon
+    else:
+      properties:
+        altr,sysmgr-syscon: false
+
 required:
   - compatible
   - reg