[v8,5/5] PCI: j721e: add j784s4 PCIe configuration
Commit Message
From: Matt Ranostay <mranostay@ti.com>
Add PCIe configuration for j784s4 platform which has 4x lane support.
Tested-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Achal Verma <a-verma1@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
Comments
If you repost for some other reason, fix the subject typo ("Add ..."
to match the others). Otherwise, Lorenzo may fix it up while
applying.
On Wed, Jan 18, 2023 at 06:29:36PM +0530, Achal Verma wrote:
> From: Matt Ranostay <mranostay@ti.com>
>
> Add PCIe configuration for j784s4 platform which has 4x lane support.
>
> Tested-by: Achal Verma <a-verma1@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Reviewed-by: Roger Quadros <rogerq@kernel.org>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
@@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
.max_lanes = 1,
};
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+ .mode = PCI_MODE_RC,
+ .quirk_retrain_flag = true,
+ .byte_access_allowed = false,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+ .mode = PCI_MODE_EP,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
static const struct of_device_id of_j721e_pcie_match[] = {
{
.compatible = "ti,j721e-pcie-host",
@@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
.compatible = "ti,am64-pcie-ep",
.data = &am64_pcie_ep_data,
},
+ {
+ .compatible = "ti,j784s4-pcie-host",
+ .data = &j784s4_pcie_rc_data,
+ },
+ {
+ .compatible = "ti,j784s4-pcie-ep",
+ .data = &j784s4_pcie_ep_data,
+ },
{},
};