diff mbox series

[V2] tty: serial: fsl_lpuart: don't break the on-going transfer when global reset

Message ID 20221019110720.31722-1-sherry.sun@nxp.com
State New
Headers
Series [V2] tty: serial: fsl_lpuart: don't break the on-going transfer when global reset |

Commit Message

Sherry Sun Oct. 19, 2022, 11:07 a.m. UTC 
  lpuart_global_reset() shouldn't break the on-going transmit engin, need
to recover the on-going data transfer after reset.

This can help earlycon here, since commit 60f361722ad2 ("serial:
fsl_lpuart: Reset prior to registration") moved lpuart_global_reset()
before uart_add_one_port(), earlycon is writing during global reset,
as global reset will disable the TX and clear the baud rate register,
which caused the earlycon cannot work any more after reset, needs to
restore the baud rate and re-enable the transmitter to recover the
earlycon write.

Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for imx7ulp and imx8qxp")
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
Changes in V2:
1. The while loop may never exit as the stat and sfifo are not re-read inside
the loop, fix that.
---
 drivers/tty/serial/fsl_lpuart.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

Comments

Shenwei Wang Oct. 19, 2022, 2:29 p.m. UTC | #1 
> -----Original Message-----
> From: Sherry Sun <sherry.sun@nxp.com>
> Sent: Wednesday, October 19, 2022 6:07 AM
> To: gregkh@linuxfoundation.org; jirislaby@kernel.org; lukas@wunner.de;
> ilpo.jarvinen@linux.intel.com
> Cc: linux-serial@vger.kernel.org; linux-kernel@vger.kernel.org; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: [PATCH V2] tty: serial: fsl_lpuart: don't break the on-going transfer
> when global reset
> 
> lpuart_global_reset() shouldn't break the on-going transmit engin, need to
> recover the on-going data transfer after reset.
> 
> This can help earlycon here, since commit 60f361722ad2 ("serial:
> fsl_lpuart: Reset prior to registration") moved lpuart_global_reset() before
> uart_add_one_port(), earlycon is writing during global reset, as global reset will
> disable the TX and clear the baud rate register, which caused the earlycon
> cannot work any more after reset, needs to restore the baud rate and re-enable
> the transmitter to recover the earlycon write.
> 
> Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for imx7ulp and
> imx8qxp")
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> Changes in V2:
> 1. The while loop may never exit as the stat and sfifo are not re-read inside the
> loop, fix that.
> ---
>  drivers/tty/serial/fsl_lpuart.c | 22 +++++++++++++++++++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index
> 67fa113f77d4..9a0781395b1f 100644
> --- a/drivers/tty/serial/fsl_lpuart.c
> +++ b/drivers/tty/serial/fsl_lpuart.c
> @@ -408,11 +408,9 @@ static int lpuart_global_reset(struct lpuart_port *sport)
> {
>  	struct uart_port *port = &sport->port;
>  	void __iomem *global_addr;
> +	unsigned long tx_enable, bd;
>  	int ret;
> 
> -	if (uart_console(port))
> -		return 0;
> -
>  	ret = clk_prepare_enable(sport->ipg_clk);
>  	if (ret) {
>  		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
> ret); @@ -420,11 +418,29 @@ static int lpuart_global_reset(struct lpuart_port
> *sport)
>  	}
> 
>  	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> +		/*
> +		 * If the transmitter is used by earlycon, wait transmit engin
> complete
> +		 * and then reset
> +		 */
> +		tx_enable = lpuart32_read(port, UARTCTRL) & UARTCTRL_TE;
> +		if (tx_enable) {
> +			bd = lpuart32_read(&sport->port, UARTBAUD);
> +			while (!(lpuart32_read(port, UARTSTAT) &
> UARTSTAT_TC &&
> +				 lpuart32_read(port, UARTFIFO) &
> UARTFIFO_TXEMPT))
> +				cpu_relax();
> +		}
> +
>  		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
>  		writel(UART_GLOBAL_RST, global_addr);
>  		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);

According to the statement in the RM, you don't need to add delay here.
"There is no minimum delay required before clearing the software reset."

>  		writel(0, global_addr);
>  		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);

[...]

Regards,
Shenwei

> +
> +		/* Recover the transmitter for earlycon */
> +		if (tx_enable) {
> +			lpuart32_write(port, bd, UARTBAUD);
> +			lpuart32_write(port, UARTCTRL_TE, UARTCTRL);
> +		}
>  	}
> 
>  	clk_disable_unprepare(sport->ipg_clk);
> --
> 2.17.1
Sherry Sun Oct. 20, 2022, 2:16 a.m. UTC | #2 
> > -----Original Message-----
> > From: Sherry Sun <sherry.sun@nxp.com>
> > Sent: Wednesday, October 19, 2022 6:07 AM
> > To: gregkh@linuxfoundation.org; jirislaby@kernel.org; lukas@wunner.de;
> > ilpo.jarvinen@linux.intel.com
> > Cc: linux-serial@vger.kernel.org; linux-kernel@vger.kernel.org;
> > dl-linux-imx <linux-imx@nxp.com>
> > Subject: [PATCH V2] tty: serial: fsl_lpuart: don't break the on-going
> > transfer when global reset
> >
> > lpuart_global_reset() shouldn't break the on-going transmit engin,
> > need to recover the on-going data transfer after reset.
> >
> > This can help earlycon here, since commit 60f361722ad2 ("serial:
> > fsl_lpuart: Reset prior to registration") moved lpuart_global_reset()
> > before uart_add_one_port(), earlycon is writing during global reset,
> > as global reset will disable the TX and clear the baud rate register,
> > which caused the earlycon cannot work any more after reset, needs to
> > restore the baud rate and re-enable the transmitter to recover the earlycon
> write.
> >
> > Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for
> > imx7ulp and
> > imx8qxp")
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > Changes in V2:
> > 1. The while loop may never exit as the stat and sfifo are not re-read
> > inside the loop, fix that.
> > ---
> >  drivers/tty/serial/fsl_lpuart.c | 22 +++++++++++++++++++---
> >  1 file changed, 19 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/tty/serial/fsl_lpuart.c
> > b/drivers/tty/serial/fsl_lpuart.c index 67fa113f77d4..9a0781395b1f
> > 100644
> > --- a/drivers/tty/serial/fsl_lpuart.c
> > +++ b/drivers/tty/serial/fsl_lpuart.c
> > @@ -408,11 +408,9 @@ static int lpuart_global_reset(struct lpuart_port
> > *sport) {
> >  	struct uart_port *port = &sport->port;
> >  	void __iomem *global_addr;
> > +	unsigned long tx_enable, bd;
> >  	int ret;
> >
> > -	if (uart_console(port))
> > -		return 0;
> > -
> >  	ret = clk_prepare_enable(sport->ipg_clk);
> >  	if (ret) {
> >  		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
> > ret); @@ -420,11 +418,29 @@ static int lpuart_global_reset(struct
> > lpuart_port
> > *sport)
> >  	}
> >
> >  	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> > +		/*
> > +		 * If the transmitter is used by earlycon, wait transmit engin
> > complete
> > +		 * and then reset
> > +		 */
> > +		tx_enable = lpuart32_read(port, UARTCTRL) & UARTCTRL_TE;
> > +		if (tx_enable) {
> > +			bd = lpuart32_read(&sport->port, UARTBAUD);
> > +			while (!(lpuart32_read(port, UARTSTAT) &
> > UARTSTAT_TC &&
> > +				 lpuart32_read(port, UARTFIFO) &
> > UARTFIFO_TXEMPT))
> > +				cpu_relax();
> > +		}
> > +
> >  		global_addr = port->membase + UART_GLOBAL -
> IMX_REG_OFF;
> >  		writel(UART_GLOBAL_RST, global_addr);
> >  		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
> 
> According to the statement in the RM, you don't need to add delay here.
> "There is no minimum delay required before clearing the software reset."
> 
Hi Shenwei,

Assuming you are referencing the imx8ulp lpuart RM, yes, for imx8ulp/imx93 lpuart, no minimum delay is required before clearing the software reset.
But for imx7ulp and imx8qxp lpuart here, the minimum delay is required before clearing the software reset, so here the usleep is needed.

Best Regards
Sherry
Jiri Slaby Oct. 20, 2022, 5:56 a.m. UTC | #3 
On 19. 10. 22, 13:07, Sherry Sun wrote:
> lpuart_global_reset() shouldn't break the on-going transmit engin, need

"engine"

> to recover the on-going data transfer after reset.
> 
> This can help earlycon here, since commit 60f361722ad2 ("serial:
> fsl_lpuart: Reset prior to registration") moved lpuart_global_reset()
> before uart_add_one_port(), earlycon is writing during global reset,
> as global reset will disable the TX and clear the baud rate register,
> which caused the earlycon cannot work any more after reset, needs to
> restore the baud rate and re-enable the transmitter to recover the
> earlycon write.
> 
> Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for imx7ulp and imx8qxp")
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> Changes in V2:
> 1. The while loop may never exit as the stat and sfifo are not re-read inside
> the loop, fix that.
> ---
>   drivers/tty/serial/fsl_lpuart.c | 22 +++++++++++++++++++---
>   1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
> index 67fa113f77d4..9a0781395b1f 100644
> --- a/drivers/tty/serial/fsl_lpuart.c
> +++ b/drivers/tty/serial/fsl_lpuart.c
> @@ -408,11 +408,9 @@ static int lpuart_global_reset(struct lpuart_port *sport)
>   {
>   	struct uart_port *port = &sport->port;
>   	void __iomem *global_addr;
> +	unsigned long tx_enable, bd;
>   	int ret;
>   
> -	if (uart_console(port))
> -		return 0;
> -
>   	ret = clk_prepare_enable(sport->ipg_clk);
>   	if (ret) {
>   		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
> @@ -420,11 +418,29 @@ static int lpuart_global_reset(struct lpuart_port *sport)
>   	}
>   
>   	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> +		/*
> +		 * If the transmitter is used by earlycon, wait transmit engin complete

"wait for transmit engine to complete"

> +		 * and then reset

"." (add a period)

> +		 */
> +		tx_enable = lpuart32_read(port, UARTCTRL) & UARTCTRL_TE;
> +		if (tx_enable) {
> +			bd = lpuart32_read(&sport->port, UARTBAUD);
> +			while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TC &&
> +				 lpuart32_read(port, UARTFIFO) & UARTFIFO_TXEMPT))
> +				cpu_relax();

If the HW is stuck, you make the kernel stuck too. What about 
read_poll_timeout_atomic(). Or at least a custom timeout.

> +		}
> +
>   		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
>   		writel(UART_GLOBAL_RST, global_addr);
>   		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
>   		writel(0, global_addr);
>   		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
> +
> +		/* Recover the transmitter for earlycon */
> +		if (tx_enable) {
> +			lpuart32_write(port, bd, UARTBAUD);
> +			lpuart32_write(port, UARTCTRL_TE, UARTCTRL);

I don't know the HW. Is it enough to write TE here? IOW shouldn't we 
preserve the whole register content from the above read here?

thanks,
Sherry Sun Oct. 20, 2022, 10:43 a.m. UTC | #4 
> On 19. 10. 22, 13:07, Sherry Sun wrote:
> > lpuart_global_reset() shouldn't break the on-going transmit engin,
> > need
> 
> "engine"

Will fix it in V3.

> 
> > to recover the on-going data transfer after reset.
> >
> > This can help earlycon here, since commit 60f361722ad2 ("serial:
> > fsl_lpuart: Reset prior to registration") moved lpuart_global_reset()
> > before uart_add_one_port(), earlycon is writing during global reset,
> > as global reset will disable the TX and clear the baud rate register,
> > which caused the earlycon cannot work any more after reset, needs to
> > restore the baud rate and re-enable the transmitter to recover the
> > earlycon write.
> >
> > Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for
> > imx7ulp and imx8qxp")
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > Changes in V2:
> > 1. The while loop may never exit as the stat and sfifo are not re-read
> > inside the loop, fix that.
> > ---
> >   drivers/tty/serial/fsl_lpuart.c | 22 +++++++++++++++++++---
> >   1 file changed, 19 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/tty/serial/fsl_lpuart.c
> > b/drivers/tty/serial/fsl_lpuart.c index 67fa113f77d4..9a0781395b1f
> > 100644
> > --- a/drivers/tty/serial/fsl_lpuart.c
> > +++ b/drivers/tty/serial/fsl_lpuart.c
> > @@ -408,11 +408,9 @@ static int lpuart_global_reset(struct lpuart_port
> *sport)
> >   {
> >   	struct uart_port *port = &sport->port;
> >   	void __iomem *global_addr;
> > +	unsigned long tx_enable, bd;
> >   	int ret;
> >
> > -	if (uart_console(port))
> > -		return 0;
> > -
> >   	ret = clk_prepare_enable(sport->ipg_clk);
> >   	if (ret) {
> >   		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
> > ret); @@ -420,11 +418,29 @@ static int lpuart_global_reset(struct
> lpuart_port *sport)
> >   	}
> >
> >   	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> > +		/*
> > +		 * If the transmitter is used by earlycon, wait transmit engin
> > +complete
> 
> "wait for transmit engine to complete"
> 
> > +		 * and then reset
> 
> "." (add a period)

Will fix it in V3. 

> 
> > +		 */
> > +		tx_enable = lpuart32_read(port, UARTCTRL) & UARTCTRL_TE;
> > +		if (tx_enable) {
> > +			bd = lpuart32_read(&sport->port, UARTBAUD);
> > +			while (!(lpuart32_read(port, UARTSTAT) &
> UARTSTAT_TC &&
> > +				 lpuart32_read(port, UARTFIFO) &
> UARTFIFO_TXEMPT))
> > +				cpu_relax();
> 
> If the HW is stuck, you make the kernel stuck too. What about
> read_poll_timeout_atomic(). Or at least a custom timeout.

Seems use read_poll_timeout_atomic() is a good idea, I will try that.

> 
> > +		}
> > +
> >   		global_addr = port->membase + UART_GLOBAL -
> IMX_REG_OFF;
> >   		writel(UART_GLOBAL_RST, global_addr);
> >   		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
> >   		writel(0, global_addr);
> >   		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
> > +
> > +		/* Recover the transmitter for earlycon */
> > +		if (tx_enable) {
> > +			lpuart32_write(port, bd, UARTBAUD);
> > +			lpuart32_write(port, UARTCTRL_TE, UARTCTRL);
> 
> I don't know the HW. Is it enough to write TE here? IOW shouldn't we
> preserve the whole register content from the above read here?

Yes, maybe restore the whole ctrl register here would be better to avoid any confusion, will do that in V3. Thanks.

Best Regards
Sherry
diff mbox series

Patch

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 67fa113f77d4..9a0781395b1f 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -408,11 +408,9 @@  static int lpuart_global_reset(struct lpuart_port *sport)
 {
 	struct uart_port *port = &sport->port;
 	void __iomem *global_addr;
+	unsigned long tx_enable, bd;
 	int ret;
 
-	if (uart_console(port))
-		return 0;
-
 	ret = clk_prepare_enable(sport->ipg_clk);
 	if (ret) {
 		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
@@ -420,11 +418,29 @@  static int lpuart_global_reset(struct lpuart_port *sport)
 	}
 
 	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
+		/*
+		 * If the transmitter is used by earlycon, wait transmit engin complete
+		 * and then reset
+		 */
+		tx_enable = lpuart32_read(port, UARTCTRL) & UARTCTRL_TE;
+		if (tx_enable) {
+			bd = lpuart32_read(&sport->port, UARTBAUD);
+			while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TC &&
+				 lpuart32_read(port, UARTFIFO) & UARTFIFO_TXEMPT))
+				cpu_relax();
+		}
+
 		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
 		writel(UART_GLOBAL_RST, global_addr);
 		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
 		writel(0, global_addr);
 		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
+
+		/* Recover the transmitter for earlycon */
+		if (tx_enable) {
+			lpuart32_write(port, bd, UARTBAUD);
+			lpuart32_write(port, UARTCTRL_TE, UARTCTRL);
+		}
 	}
 
 	clk_disable_unprepare(sport->ipg_clk);