diff mbox series

[v5,5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index()

Message ID 20221128164028.4570-6-xin3.li@intel.com
State New
Headers
Series x86: Enable LKGS instruction |

Commit Message

Li, Xin3 Nov. 28, 2022, 4:40 p.m. UTC 
  From: "H. Peter Anvin (Intel)" <hpa@zytor.com>

The LKGS instruction atomically loads a segment descriptor into the
%gs descriptor registers, *except* that %gs.base is unchanged, and the
base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
what we want this function to do.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Brian Gerst <brgerst@gmail.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
---

Changes since v4:
* Clear the LKGS feature from Xen PV guests (Juergen Gross).

Changes since v3:
* We want less ASM not more, thus keep local_irq_save/restore() inside
  native_load_gs_index() (Thomas Gleixner).
* For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to
  native_lkgs (Thomas Gleixner).

Changes since v2:
* Mark DI as input and output (+D) as in V1, since the exception handler
  modifies it (Brian Gerst).

Changes since v1:
* Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code
  section (Peter Zijlstra).
* Add a comment that states the LKGS_DI macro will be repalced with "lkgs %di"
  once the binutils support the LKGS instruction (Peter Zijlstra).
---
 arch/x86/include/asm/gsseg.h | 33 +++++++++++++++++++++++++++++----
 arch/x86/kernel/cpu/common.c |  1 +
 arch/x86/xen/enlighten_pv.c  |  1 +
 3 files changed, 31 insertions(+), 4 deletions(-)

Comments

Borislav Petkov Jan. 11, 2023, 2:30 p.m. UTC | #1 
On Mon, Nov 28, 2022 at 08:40:28AM -0800, Xin Li wrote:
> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
> 
> The LKGS instruction atomically loads a segment descriptor into the
> %gs descriptor registers, *except* that %gs.base is unchanged, and the
> base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
> what we want this function to do.
> 
> Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> Signed-off-by: Brian Gerst <brgerst@gmail.com>
> Signed-off-by: Juergen Gross <jgross@suse.com>
> Signed-off-by: Xin Li <xin3.li@intel.com>

I'm reading this SOB chain as

hpa wrote it -> then it went to Peter -> then to Brian -> then to Juergen -> and
you're sending it.

I'm pretty sure that cannot be right.

> ---
> 
> Changes since v4:
> * Clear the LKGS feature from Xen PV guests (Juergen Gross).
> 
> Changes since v3:
> * We want less ASM not more, thus keep local_irq_save/restore() inside
>   native_load_gs_index() (Thomas Gleixner).
> * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to
>   native_lkgs (Thomas Gleixner).
> 
> Changes since v2:
> * Mark DI as input and output (+D) as in V1, since the exception handler
>   modifies it (Brian Gerst).
> 
> Changes since v1:
> * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code
>   section (Peter Zijlstra).
> * Add a comment that states the LKGS_DI macro will be repalced with "lkgs %di"
>   once the binutils support the LKGS instruction (Peter Zijlstra).

I guess that explains what the SOB chain is supposed to mean - you've gotten
review feedback. But that doesn't need such a SOB chain. Sounds like you need to
refresh on

Documentation/process/submitting-patches.rst

Thx.
Li, Xin3 Jan. 11, 2023, 6:22 p.m. UTC | #2 
> > The LKGS instruction atomically loads a segment descriptor into the
> > %gs descriptor registers, *except* that %gs.base is unchanged, and the
> > base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
> > what we want this function to do.
> >
> > Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
> > Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> > Signed-off-by: Brian Gerst <brgerst@gmail.com>
> > Signed-off-by: Juergen Gross <jgross@suse.com>
> > Signed-off-by: Xin Li <xin3.li@intel.com>
> 
> I'm reading this SOB chain as
> 
> hpa wrote it -> then it went to Peter -> then to Brian -> then to Juergen -> and
> you're sending it.
> 
> I'm pretty sure that cannot be right.
> 
> > ---
> >
> > Changes since v4:
> > * Clear the LKGS feature from Xen PV guests (Juergen Gross).
> >
> > Changes since v3:
> > * We want less ASM not more, thus keep local_irq_save/restore() inside
> >   native_load_gs_index() (Thomas Gleixner).
> > * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to
> >   native_lkgs (Thomas Gleixner).
> >
> > Changes since v2:
> > * Mark DI as input and output (+D) as in V1, since the exception handler
> >   modifies it (Brian Gerst).
> >
> > Changes since v1:
> > * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code
> >   section (Peter Zijlstra).
> > * Add a comment that states the LKGS_DI macro will be repalced with "lkgs
> %di"
> >   once the binutils support the LKGS instruction (Peter Zijlstra).
> 
> I guess that explains what the SOB chain is supposed to mean - you've gotten
> review feedback. But that doesn't need such a SOB chain. Sounds like you need
> to refresh on

Your guess is correct, will remove those SOBs in v6.

> Documentation/process/submitting-patches.rst
> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> https://people.kernel.org/tglx/notes-about-netiquette
diff mbox series

Patch

diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h
index d15577c39e8d..ab6a595cea70 100644
--- a/arch/x86/include/asm/gsseg.h
+++ b/arch/x86/include/asm/gsseg.h
@@ -14,17 +14,42 @@ 
 
 extern asmlinkage void asm_load_gs_index(u16 selector);
 
+/* Replace with "lkgs %di" once binutils support LKGS instruction */
+#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7)
+
+static inline void native_lkgs(unsigned int selector)
+{
+	u16 sel = selector;
+	asm_inline volatile("1: " LKGS_DI
+			    _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel])
+			    : [sel] "+D" (sel));
+}
+
 static inline void native_load_gs_index(unsigned int selector)
 {
-	unsigned long flags;
+	if (cpu_feature_enabled(X86_FEATURE_LKGS)) {
+		native_lkgs(selector);
+	} else {
+		unsigned long flags;
 
-	local_irq_save(flags);
-	asm_load_gs_index(selector);
-	local_irq_restore(flags);
+		local_irq_save(flags);
+		asm_load_gs_index(selector);
+		local_irq_restore(flags);
+	}
 }
 
 #endif /* CONFIG_X86_64 */
 
+static inline void __init lkgs_init(void)
+{
+#ifdef CONFIG_PARAVIRT_XXL
+#ifdef CONFIG_X86_64
+	if (cpu_feature_enabled(X86_FEATURE_LKGS))
+		pv_ops.cpu.load_gs_index = native_lkgs;
+#endif
+#endif
+}
+
 #ifndef CONFIG_PARAVIRT_XXL
 
 static inline void load_gs_index(unsigned int selector)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3e508f239098..d6eb4f60b47d 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1939,6 +1939,7 @@  void __init identify_boot_cpu(void)
 	setup_cr_pinning();
 
 	tsx_init();
+	lkgs_init();
 }
 
 void identify_secondary_cpu(struct cpuinfo_x86 *c)
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index 038da45f057a..c48a9061160e 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -276,6 +276,7 @@  static void __init xen_init_capabilities(void)
 	setup_clear_cpu_cap(X86_FEATURE_ACC);
 	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
 	setup_clear_cpu_cap(X86_FEATURE_SME);
+	setup_clear_cpu_cap(X86_FEATURE_LKGS);
 
 	/*
 	 * Xen PV would need some work to support PCID: CR3 handling as well