Message ID | 20221215025402.1733132-1-chris.packham@alliedtelesis.co.nz |
---|---|
State | New |
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Series |
arm64: dts: marvell: AC5/AC5X: Fix address for UART1
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Commit Message
Chris Packham
Dec. 15, 2022, 2:54 a.m. UTC
The correct address offset is 0x12100.
Fixes: 31be791e26cf ("arm64: dts: marvell: Add UART1-3 for AC5/AC5X")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Not sure how this happened. I only noticed when I had a conflict in some
local patches I was rebasing against upstream. So I obviously had it
right at one point but then managed to break it in the process of
cleaning things up for submission.
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
Hi All, On 15/12/22 15:54, Chris Packham wrote: > The correct address offset is 0x12100. > > Fixes: 31be791e26cf ("arm64: dts: marvell: Add UART1-3 for AC5/AC5X") > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > Not sure how this happened. I only noticed when I had a conflict in some > local patches I was rebasing against upstream. So I obviously had it > right at one point but then managed to break it in the process of > cleaning things up for submission. I know people have probably been away with various holidays but I think it's been long enough so.... ping? > > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > index 7308f7b6b22c..8bce64069138 100644 > --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > @@ -98,7 +98,7 @@ uart0: serial@12000 { > > uart1: serial@12100 { > compatible = "snps,dw-apb-uart"; > - reg = <0x11000 0x100>; > + reg = <0x12100 0x100>; > reg-shift = <2>; > interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > reg-io-width = <1>;
Chris Packham <Chris.Packham@alliedtelesis.co.nz> writes: > Hi All, > > On 15/12/22 15:54, Chris Packham wrote: >> The correct address offset is 0x12100. >> >> Fixes: 31be791e26cf ("arm64: dts: marvell: Add UART1-3 for AC5/AC5X") >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> --- >> Not sure how this happened. I only noticed when I had a conflict in some >> local patches I was rebasing against upstream. So I obviously had it >> right at one point but then managed to break it in the process of >> cleaning things up for submission. > > I know people have probably been away with various holidays but I think > it's been long enough so.... > > ping? Applied on mvebu/fixes Thanks, Gregory > >> >> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi >> index 7308f7b6b22c..8bce64069138 100644 >> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi >> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi >> @@ -98,7 +98,7 @@ uart0: serial@12000 { >> >> uart1: serial@12100 { >> compatible = "snps,dw-apb-uart"; >> - reg = <0x11000 0x100>; >> + reg = <0x12100 0x100>; >> reg-shift = <2>; >> interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; >> reg-io-width = <1>;
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 7308f7b6b22c..8bce64069138 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -98,7 +98,7 @@ uart0: serial@12000 { uart1: serial@12100 { compatible = "snps,dw-apb-uart"; - reg = <0x11000 0x100>; + reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>;