diff mbox series

[1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge

Message ID 20221019144640.9458-1-thippeswamy.havalige@amd.com
State New
Headers
Series [1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge |

Commit Message

Havalige, Thippeswamy Oct. 19, 2022, 2:46 p.m. UTC 
  Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge
dt binding.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
---
 .../devicetree/bindings/pci/xilinx-pcie.txt   | 88 -------------------
 .../devicetree/bindings/pci/xilinx-pcie.yaml  | 81 +++++++++++++++++
 2 files changed, 81 insertions(+), 88 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.yaml

Comments

Krzysztof Kozlowski Oct. 19, 2022, 3:04 p.m. UTC | #1 
On 19/10/2022 10:46, Thippeswamy Havalige wrote:
> Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge
> dt binding.
> 
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> ---
>  .../devicetree/bindings/pci/xilinx-pcie.txt   | 88 -------------------
>  .../devicetree/bindings/pci/xilinx-pcie.yaml  | 81 +++++++++++++++++
>  2 files changed, 81 insertions(+), 88 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
>  create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> deleted file mode 100644
> index fd57a81180a4..000000000000
> --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -* Xilinx AXI PCIe Root Port Bridge DT description
> -
> -Required properties:
> -- #address-cells: Address representation for root ports, set to <3>
> -- #size-cells: Size representation for root ports, set to <2>
> -- #interrupt-cells: specifies the number of cells needed to encode an
> -	interrupt source. The value must be 1.
> -- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
> -- reg: Should contain AXI PCIe registers location and length
> -- device_type: must be "pci"
> -- interrupts: Should contain AXI PCIe interrupt
> -- interrupt-map-mask,
> -  interrupt-map: standard PCI properties to define the mapping of the
> -	PCI interface to interrupt numbers.
> -- ranges: ranges for the PCI memory regions (I/O space region is not
> -	supported by hardware)
> -	Please refer to the standard PCI bus binding document for a more
> -	detailed explanation
> -
> -Optional properties for Zynq/Microblaze:
> -- bus-range: PCI bus numbers covered
> -
> -Interrupt controller child node
> -+++++++++++++++++++++++++++++++
> -Required properties:
> -- interrupt-controller: identifies the node as an interrupt controller
> -- #address-cells: specifies the number of cells needed to encode an
> -	address. The value must be 0.
> -- #interrupt-cells: specifies the number of cells needed to encode an
> -	interrupt source. The value must be 1.
> -
> -NOTE:
> -The core provides a single interrupt for both INTx/MSI messages. So,
> -created a interrupt controller node to support 'interrupt-map' DT
> -functionality.  The driver will create an IRQ domain for this map, decode
> -the four INTx interrupts in ISR and route them to this domain.
> -
> -
> -Example:
> -++++++++
> -Zynq:
> -	pci_express: axi-pcie@50000000 {
> -		#address-cells = <3>;
> -		#size-cells = <2>;
> -		#interrupt-cells = <1>;
> -		compatible = "xlnx,axi-pcie-host-1.00.a";
> -		reg = < 0x50000000 0x1000000 >;
> -		device_type = "pci";
> -		interrupts = < 0 52 4 >;
> -		interrupt-map-mask = <0 0 0 7>;
> -		interrupt-map = <0 0 0 1 &pcie_intc 1>,
> -				<0 0 0 2 &pcie_intc 2>,
> -				<0 0 0 3 &pcie_intc 3>,
> -				<0 0 0 4 &pcie_intc 4>;
> -		ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
> -
> -		pcie_intc: interrupt-controller {
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <1>;
> -		};
> -	};
> -
> -
> -Microblaze:
> -	pci_express: axi-pcie@10000000 {
> -		#address-cells = <3>;
> -		#size-cells = <2>;
> -		#interrupt-cells = <1>;
> -		compatible = "xlnx,axi-pcie-host-1.00.a";
> -		reg = <0x10000000 0x4000000>;
> -		device_type = "pci";
> -		interrupt-parent = <&microblaze_0_intc>;
> -		interrupts = <1 2>;
> -		interrupt-map-mask = <0 0 0 7>;
> -		interrupt-map = <0 0 0 1 &pcie_intc 1>,
> -				<0 0 0 2 &pcie_intc 2>,
> -				<0 0 0 3 &pcie_intc 3>,
> -				<0 0 0 4 &pcie_intc 4>;
> -		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
> -
> -		pcie_intc: interrupt-controller {
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <1>;
> -		};
> -
> -	};
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
> new file mode 100644
> index 000000000000..6b372ac1763e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/xilinx-pcie.yaml#

Filename based on compatible, so:
xlnx,axi-pcie-host.yaml

> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx AXI PCIe Root Port Bridge DT description

Drop "DT description"

> +
> +maintainers:
> +  - Thippeswamy Havalige <thippesw@xilinx.com>
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    const: xlnx,axi-pcie-host-1.00.a
> +
> +  reg:
> +    items:
> +      - description: should contain AXI PCIe registers location and length

Drop description, just maxItems: 1

> +
> +  interrupts:
> +    items:
> +      - description: should contain AXI PCIe interrupt

Ditto


> +
> +  ranges:
> +    items:
> +      - description: |
> +          ranges for the PCI memory regions (I/O space region is not
> +          supported by hardware)
> +
> +  "#interrupt-cells":
> +    const: 1
> +
> +  interrupt-controller:
> +    description: identifies the node as an interrupt controller
> +    type: object

    additionalProperties: false

> +    properties:
> +      "interrupt-controller": true
> +      "#address-cells":
> +        const: 0
> +      "#interrupt-cells":
> +        const: 1

Add also required properties for this node.

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - ranges
> +  - device_type
> +  - interrupt-map
> +  - "#interrupt-cells"
> +  - interrupt-controller
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +
> +    Zynq:
> +        pci_express: pcie@50000000 {
> +               #address-cells = <3>;

Use 4 spaces for example indentation.

> +               #size-cells = <2>;
> +               #interrupt-cells = <1>;
> +               compatible = "xlnx,axi-pcie-host-1.00.a";
> +               reg = < 0x50000000 0x1000000 >;

Fix style.

compatible goes first, then reg, then the rest.

> +               device_type = "pci";
> +               interrupts = < 0 52 4 >;

Fix the style, use defines.

> +               interrupt-map-mask = <0 0 0 7>;
> +               interrupt-map = <0 0 0 1 &pcie_intc 1>,
> +                               <0 0 0 2 &pcie_intc 2>,
> +                               <0 0 0 3 &pcie_intc 3>,
> +                               <0 0 0 4 &pcie_intc 4>;
> +                ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;

Original example looked correct, so how did it become with these spaces?

> +                pcie_intc: interrupt-controller {
> +                         interrupt-controller;
> +                         #address-cells = <0>;
> +                         #interrupt-cells = <1>;
> +                };
> +    };

Best regards,
Krzysztof
Krzysztof Kozlowski Oct. 19, 2022, 3:11 p.m. UTC | #2 
On 19/10/2022 10:46, Thippeswamy Havalige wrote:
> Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge
> dt binding.


> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - ranges
> +  - device_type

Drop all properties which are already required by referenced schemas.

> +  - interrupt-map
> +  - "#interrupt-cells"
> +  - interrupt-controller
> +


Best regards,
Krzysztof
Havalige, Thippeswamy Oct. 25, 2022, 2:02 p.m. UTC | #3 
Hi,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, October 19, 2022 8:34 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; linux-
> pci@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; krzysztof.kozlowski+dt@linaro.org
> Cc: bhelgaas@google.com; michals@xilinx.com; robh+dt@kernel.org;
> Gogada, Bharat Kumar <bharat.kumar.gogada@amd.com>
> Subject: Re: [PATCH 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML
> schemas of Xilinx AXI PCIe Root Port Bridge
> 
> On 19/10/2022 10:46, Thippeswamy Havalige wrote:
> > Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge dt
> > binding.
> >
> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> > ---
> >  .../devicetree/bindings/pci/xilinx-pcie.txt   | 88 -------------------
> >  .../devicetree/bindings/pci/xilinx-pcie.yaml  | 81 +++++++++++++++++
> >  2 files changed, 81 insertions(+), 88 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> > b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> > deleted file mode 100644
> > index fd57a81180a4..000000000000
> > --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> > +++ /dev/null
> > @@ -1,88 +0,0 @@
> > -* Xilinx AXI PCIe Root Port Bridge DT description
> > -
> > -Required properties:
> > -- #address-cells: Address representation for root ports, set to <3>
> > -- #size-cells: Size representation for root ports, set to <2>
> > -- #interrupt-cells: specifies the number of cells needed to encode an
> > -	interrupt source. The value must be 1.
> > -- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
> > -- reg: Should contain AXI PCIe registers location and length
> > -- device_type: must be "pci"
> > -- interrupts: Should contain AXI PCIe interrupt
> > -- interrupt-map-mask,
> > -  interrupt-map: standard PCI properties to define the mapping of the
> > -	PCI interface to interrupt numbers.
> > -- ranges: ranges for the PCI memory regions (I/O space region is not
> > -	supported by hardware)
> > -	Please refer to the standard PCI bus binding document for a more
> > -	detailed explanation
> > -
> > -Optional properties for Zynq/Microblaze:
> > -- bus-range: PCI bus numbers covered
> > -
> > -Interrupt controller child node
> > -+++++++++++++++++++++++++++++++
> > -Required properties:
> > -- interrupt-controller: identifies the node as an interrupt
> > controller
> > -- #address-cells: specifies the number of cells needed to encode an
> > -	address. The value must be 0.
> > -- #interrupt-cells: specifies the number of cells needed to encode an
> > -	interrupt source. The value must be 1.
> > -
> > -NOTE:
> > -The core provides a single interrupt for both INTx/MSI messages. So,
> > -created a interrupt controller node to support 'interrupt-map' DT
> > -functionality.  The driver will create an IRQ domain for this map,
> > decode -the four INTx interrupts in ISR and route them to this domain.
> > -
> > -
> > -Example:
> > -++++++++
> > -Zynq:
> > -	pci_express: axi-pcie@50000000 {
> > -		#address-cells = <3>;
> > -		#size-cells = <2>;
> > -		#interrupt-cells = <1>;
> > -		compatible = "xlnx,axi-pcie-host-1.00.a";
> > -		reg = < 0x50000000 0x1000000 >;
> > -		device_type = "pci";
> > -		interrupts = < 0 52 4 >;
> > -		interrupt-map-mask = <0 0 0 7>;
> > -		interrupt-map = <0 0 0 1 &pcie_intc 1>,
> > -				<0 0 0 2 &pcie_intc 2>,
> > -				<0 0 0 3 &pcie_intc 3>,
> > -				<0 0 0 4 &pcie_intc 4>;
> > -		ranges = < 0x02000000 0 0x60000000 0x60000000 0
> 0x10000000 >;
> > -
> > -		pcie_intc: interrupt-controller {
> > -			interrupt-controller;
> > -			#address-cells = <0>;
> > -			#interrupt-cells = <1>;
> > -		};
> > -	};
> > -
> > -
> > -Microblaze:
> > -	pci_express: axi-pcie@10000000 {
> > -		#address-cells = <3>;
> > -		#size-cells = <2>;
> > -		#interrupt-cells = <1>;
> > -		compatible = "xlnx,axi-pcie-host-1.00.a";
> > -		reg = <0x10000000 0x4000000>;
> > -		device_type = "pci";
> > -		interrupt-parent = <&microblaze_0_intc>;
> > -		interrupts = <1 2>;
> > -		interrupt-map-mask = <0 0 0 7>;
> > -		interrupt-map = <0 0 0 1 &pcie_intc 1>,
> > -				<0 0 0 2 &pcie_intc 2>,
> > -				<0 0 0 3 &pcie_intc 3>,
> > -				<0 0 0 4 &pcie_intc 4>;
> > -		ranges = <0x02000000 0x00000000 0x80000000 0x80000000
> 0x00000000 0x10000000>;
> > -
> > -		pcie_intc: interrupt-controller {
> > -			interrupt-controller;
> > -			#address-cells = <0>;
> > -			#interrupt-cells = <1>;
> > -		};
> > -
> > -	};
> > diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
> > new file mode 100644
> > index 000000000000..6b372ac1763e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/xilinx-pcie.yaml#
> 
> Filename based on compatible, so:
> xlnx,axi-pcie-host.yaml
> 
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx AXI PCIe Root Port Bridge DT description
> 
> Drop "DT description"
> 
> > +
> > +maintainers:
> > +  - Thippeswamy Havalige <thippesw@xilinx.com>
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    const: xlnx,axi-pcie-host-1.00.a
> > +
> > +  reg:
> > +    items:
> > +      - description: should contain AXI PCIe registers location and
> > + length
> 
> Drop description, just maxItems: 1
> 
> > +
> > +  interrupts:
> > +    items:
> > +      - description: should contain AXI PCIe interrupt
> 
> Ditto
> 
> 
> > +
> > +  ranges:
> > +    items:
> > +      - description: |
> > +          ranges for the PCI memory regions (I/O space region is not
> > +          supported by hardware)
> > +
> > +  "#interrupt-cells":
> > +    const: 1
> > +
> > +  interrupt-controller:
> > +    description: identifies the node as an interrupt controller
> > +    type: object
> 
>     additionalProperties: false
> 
> > +    properties:
> > +      "interrupt-controller": true
> > +      "#address-cells":
> > +        const: 0
> > +      "#interrupt-cells":
> > +        const: 1
> 
> Add also required properties for this node.
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - ranges
> > +  - device_type
> > +  - interrupt-map
> > +  - "#interrupt-cells"
> > +  - interrupt-controller
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    Zynq:
> > +        pci_express: pcie@50000000 {
> > +               #address-cells = <3>;
> 
> Use 4 spaces for example indentation.
> 
> > +               #size-cells = <2>;
> > +               #interrupt-cells = <1>;
> > +               compatible = "xlnx,axi-pcie-host-1.00.a";
> > +               reg = < 0x50000000 0x1000000 >;
> 
> Fix style.
> 
> compatible goes first, then reg, then the rest.
> 
> > +               device_type = "pci";
> > +               interrupts = < 0 52 4 >;
> 
> Fix the style, use defines.
> 
> > +               interrupt-map-mask = <0 0 0 7>;
> > +               interrupt-map = <0 0 0 1 &pcie_intc 1>,
> > +                               <0 0 0 2 &pcie_intc 2>,
> > +                               <0 0 0 3 &pcie_intc 3>,
> > +                               <0 0 0 4 &pcie_intc 4>;
> > +                ranges = < 0x02000000 0 0x60000000 0x60000000 0
> > + 0x10000000 >;
> 
> Original example looked correct, so how did it become with these spaces?
> 
> > +                pcie_intc: interrupt-controller {
> > +                         interrupt-controller;
> > +                         #address-cells = <0>;
> > +                         #interrupt-cells = <1>;
> > +                };
> > +    };
> 
> Best regards,
> Krzysztof

Thanks for reviewing, I agree with all the recommended changes.  I'll send updated patches.

Regards,
Thippeswamy H
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
deleted file mode 100644
index fd57a81180a4..000000000000
--- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
+++ /dev/null
@@ -1,88 +0,0 @@ 
-* Xilinx AXI PCIe Root Port Bridge DT description
-
-Required properties:
-- #address-cells: Address representation for root ports, set to <3>
-- #size-cells: Size representation for root ports, set to <2>
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
-- reg: Should contain AXI PCIe registers location and length
-- device_type: must be "pci"
-- interrupts: Should contain AXI PCIe interrupt
-- interrupt-map-mask,
-  interrupt-map: standard PCI properties to define the mapping of the
-	PCI interface to interrupt numbers.
-- ranges: ranges for the PCI memory regions (I/O space region is not
-	supported by hardware)
-	Please refer to the standard PCI bus binding document for a more
-	detailed explanation
-
-Optional properties for Zynq/Microblaze:
-- bus-range: PCI bus numbers covered
-
-Interrupt controller child node
-+++++++++++++++++++++++++++++++
-Required properties:
-- interrupt-controller: identifies the node as an interrupt controller
-- #address-cells: specifies the number of cells needed to encode an
-	address. The value must be 0.
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-
-NOTE:
-The core provides a single interrupt for both INTx/MSI messages. So,
-created a interrupt controller node to support 'interrupt-map' DT
-functionality.  The driver will create an IRQ domain for this map, decode
-the four INTx interrupts in ISR and route them to this domain.
-
-
-Example:
-++++++++
-Zynq:
-	pci_express: axi-pcie@50000000 {
-		#address-cells = <3>;
-		#size-cells = <2>;
-		#interrupt-cells = <1>;
-		compatible = "xlnx,axi-pcie-host-1.00.a";
-		reg = < 0x50000000 0x1000000 >;
-		device_type = "pci";
-		interrupts = < 0 52 4 >;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_intc 1>,
-				<0 0 0 2 &pcie_intc 2>,
-				<0 0 0 3 &pcie_intc 3>,
-				<0 0 0 4 &pcie_intc 4>;
-		ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
-
-		pcie_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-	};
-
-
-Microblaze:
-	pci_express: axi-pcie@10000000 {
-		#address-cells = <3>;
-		#size-cells = <2>;
-		#interrupt-cells = <1>;
-		compatible = "xlnx,axi-pcie-host-1.00.a";
-		reg = <0x10000000 0x4000000>;
-		device_type = "pci";
-		interrupt-parent = <&microblaze_0_intc>;
-		interrupts = <1 2>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_intc 1>,
-				<0 0 0 2 &pcie_intc 2>,
-				<0 0 0 3 &pcie_intc 3>,
-				<0 0 0 4 &pcie_intc 4>;
-		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
-
-		pcie_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-
-	};
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
new file mode 100644
index 000000000000..6b372ac1763e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml
@@ -0,0 +1,81 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/xilinx-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AXI PCIe Root Port Bridge DT description
+
+maintainers:
+  - Thippeswamy Havalige <thippesw@xilinx.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: xlnx,axi-pcie-host-1.00.a
+
+  reg:
+    items:
+      - description: should contain AXI PCIe registers location and length
+
+  interrupts:
+    items:
+      - description: should contain AXI PCIe interrupt
+
+  ranges:
+    items:
+      - description: |
+          ranges for the PCI memory regions (I/O space region is not
+          supported by hardware)
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupt-controller:
+    description: identifies the node as an interrupt controller
+    type: object
+    properties:
+      "interrupt-controller": true
+      "#address-cells":
+        const: 0
+      "#interrupt-cells":
+        const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ranges
+  - device_type
+  - interrupt-map
+  - "#interrupt-cells"
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+
+    Zynq:
+        pci_express: pcie@50000000 {
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               compatible = "xlnx,axi-pcie-host-1.00.a";
+               reg = < 0x50000000 0x1000000 >;
+               device_type = "pci";
+               interrupts = < 0 52 4 >;
+               interrupt-map-mask = <0 0 0 7>;
+               interrupt-map = <0 0 0 1 &pcie_intc 1>,
+                               <0 0 0 2 &pcie_intc 2>,
+                               <0 0 0 3 &pcie_intc 3>,
+                               <0 0 0 4 &pcie_intc 4>;
+                ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
+                pcie_intc: interrupt-controller {
+                         interrupt-controller;
+                         #address-cells = <0>;
+                         #interrupt-cells = <1>;
+                };
+    };