Message ID | 20221018162812.69673-2-akhilrajeev@nvidia.com |
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State | New |
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Tue, 18 Oct 2022 09:28:35 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 18 Oct 2022 09:28:35 -0700 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Tue, 18 Oct 2022 09:28:32 -0700 From: Akhil R <akhilrajeev@nvidia.com> To: <ldewangan@nvidia.com>, <jonathanh@nvidia.com>, <vkoul@kernel.org>, <thierry.reding@gmail.com>, <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org> CC: <akhilrajeev@nvidia.com> Subject: [PATCH RESEND v2 1/3] dt-bindings: dmaengine: Add dma-channel-mask to Tegra GPCDMA Date: Tue, 18 Oct 2022 21:58:10 +0530 Message-ID: <20221018162812.69673-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221018162812.69673-1-akhilrajeev@nvidia.com> References: <20221018162812.69673-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT018:EE_|MN0PR12MB5907:EE_ X-MS-Office365-Filtering-Correlation-Id: e3975ff4-ee76-40f2-8aea-08dab125d636 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Tegra GCPDMA: Add dma-channel-mask support
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Commit Message
Akhil R
Oct. 18, 2022, 4:28 p.m. UTC
Add dma-channel-mask property in Tegra GPCDMA document. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. Now since we can list all 32 channels, update the interrupts property as well to list all 32 interrupts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
Comments
On 18-10-22, 21:58, Akhil R wrote: > Add dma-channel-mask property in Tegra GPCDMA document. > > The property would help to specify the channels to be used in > kernel and reserve few for the firmware. This was previously > achieved by limiting the channel number to 31 in the driver. > Now since we can list all 32 channels, update the interrupts > property as well to list all 32 interrupts. Pls cc dt folks and ML on DT patches! > > Signed-off-by: Akhil R <akhilrajeev@nvidia.com> > Acked-by: Thierry Reding <treding@nvidia.com> > --- > .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > index c8894476b6ab..851bd50ee67f 100644 > --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > @@ -39,7 +39,7 @@ properties: > Should contain all of the per-channel DMA interrupts in > ascending order with respect to the DMA channel index. > minItems: 1 > - maxItems: 31 > + maxItems: 32 > > resets: > maxItems: 1 > @@ -52,6 +52,9 @@ properties: > > dma-coherent: true > > + dma-channel-mask: > + maxItems: 1 > + > required: > - compatible > - reg > @@ -60,6 +63,7 @@ required: > - reset-names > - "#dma-cells" > - iommus > + - dma-channel-mask > > additionalProperties: false > > @@ -108,5 +112,6 @@ examples: > #dma-cells = <1>; > iommus = <&smmu TEGRA186_SID_GPCDMA_0>; > dma-coherent; > + dma-channel-mask = <0xfffffffe>; > }; > ... > -- > 2.17.1
> On 18-10-22, 21:58, Akhil R wrote: > > Add dma-channel-mask property in Tegra GPCDMA document. > > > > The property would help to specify the channels to be used in kernel > > and reserve few for the firmware. This was previously achieved by > > limiting the channel number to 31 in the driver. > > Now since we can list all 32 channels, update the interrupts property > > as well to list all 32 interrupts. > > Pls cc dt folks and ML on DT patches! > Thanks for pointing. Resent the series with DT folks included. Best Regards, Akhil
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index c8894476b6ab..851bd50ee67f 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -39,7 +39,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 31 + maxItems: 32 resets: maxItems: 1 @@ -52,6 +52,9 @@ properties: dma-coherent: true + dma-channel-mask: + maxItems: 1 + required: - compatible - reg @@ -60,6 +63,7 @@ required: - reset-names - "#dma-cells" - iommus + - dma-channel-mask additionalProperties: false @@ -108,5 +112,6 @@ examples: #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; }; ...