Message ID | 20221224141700.20891-1-quic_jinlmao@quicinc.com |
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State | New |
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Sat, 24 Dec 2022 14:17:20 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BOEHJJE025679 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 24 Dec 2022 14:17:19 GMT Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 24 Dec 2022 06:17:16 -0800 From: Mao Jinlong <quic_jinlmao@quicinc.com> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>, Alexander Shishkin <alexander.shishkin@linux.intel.com> CC: Mao Jinlong <quic_jinlmao@quicinc.com>, <coresight@lists.linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Tingwei <quic_tingweiz@quicinc.com>, Yuanfang Zhang <quic_yuanfang@quicinc.com>, Tao Zhang <quic_taozha@quicinc.com>, Hao Zhang <quic_hazha@quicinc.com>, <linux-arm-msm@vger.kernel.org> Subject: [PATCH] coresight: cti: Add PM runtime call in enable_store Date: Sat, 24 Dec 2022 22:17:00 +0800 Message-ID: <20221224141700.20891-1-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KV26Nt-TXqsfPjBy2G7NHCkG8XcOWXKd X-Proofpoint-GUID: KV26Nt-TXqsfPjBy2G7NHCkG8XcOWXKd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-24_06,2022-12-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212240119 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753106806447594391?= X-GMAIL-MSGID: =?utf-8?q?1753106806447594391?= |
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coresight: cti: Add PM runtime call in enable_store
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Commit Message
Mao Jinlong
Dec. 24, 2022, 2:17 p.m. UTC
In commit 6746eae4bbad ("coresight: cti: Fix hang in cti_disable_hw()")
PM runtime calls are removed from cti_enable_hw/cti_disable_hw. When
enabling CTI by writing enable sysfs node, clock for accessing CTI
register won't be enabled. Device will crash due to register access
issue. Add PM runtime call in enable_store to fix this issue.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/coresight-cti-sysfs.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
Comments
On 24/12/2022 14:17, Mao Jinlong wrote: > In commit 6746eae4bbad ("coresight: cti: Fix hang in cti_disable_hw()") > PM runtime calls are removed from cti_enable_hw/cti_disable_hw. When > enabling CTI by writing enable sysfs node, clock for accessing CTI > register won't be enabled. Device will crash due to register access > issue. Add PM runtime call in enable_store to fix this issue. > > Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> > --- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index 6d59c815ecf5..b1ed424ae043 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -108,10 +108,17 @@ static ssize_t enable_store(struct device *dev, > if (ret) > return ret; > > - if (val) > + if (val) { > + ret = pm_runtime_resume_and_get(dev->parent); > + if (ret) > + return ret; > ret = cti_enable(drvdata->csdev); > - else > + if (ret) > + pm_runtime_put(dev->parent); > + } else { > ret = cti_disable(drvdata->csdev); > + pm_runtime_put(dev->parent); Hi Jinlong, This new pm_runtime_put() causes this when writing 0 to enable: [ 483.253814] coresight-cti 23020000.cti: Runtime PM usage count underflow! Maybe we can modify cti_disable_hw() to return a value to indicate that the disable actually happened, and only then call pm_runtime_put(). I suppose you could also check in the store function if it was already enabled first, but then I don't know what kind of locking that would need? cti_disable_hw() already seems to have a couple of locks, so maybe the return value solution is easiest. Thanks James
On 04/01/2023 13:11, James Clark wrote: > > > On 24/12/2022 14:17, Mao Jinlong wrote: >> In commit 6746eae4bbad ("coresight: cti: Fix hang in cti_disable_hw()") >> PM runtime calls are removed from cti_enable_hw/cti_disable_hw. When >> enabling CTI by writing enable sysfs node, clock for accessing CTI >> register won't be enabled. Device will crash due to register access >> issue. Add PM runtime call in enable_store to fix this issue. >> >> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> >> --- >> drivers/hwtracing/coresight/coresight-cti-sysfs.c | 11 +++++++++-- >> 1 file changed, 9 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c >> index 6d59c815ecf5..b1ed424ae043 100644 >> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c >> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c >> @@ -108,10 +108,17 @@ static ssize_t enable_store(struct device *dev, >> if (ret) >> return ret; >> >> - if (val) >> + if (val) { >> + ret = pm_runtime_resume_and_get(dev->parent); >> + if (ret) >> + return ret; >> ret = cti_enable(drvdata->csdev); >> - else >> + if (ret) >> + pm_runtime_put(dev->parent); >> + } else { >> ret = cti_disable(drvdata->csdev); >> + pm_runtime_put(dev->parent); > > Hi Jinlong, > > This new pm_runtime_put() causes this when writing 0 to enable: > > [ 483.253814] coresight-cti 23020000.cti: Runtime PM usage count > underflow! > > Maybe we can modify cti_disable_hw() to return a value to indicate that > the disable actually happened, and only then call pm_runtime_put(). > > I suppose you could also check in the store function if it was already > enabled first, but then I don't know what kind of locking that would > need? cti_disable_hw() already seems to have a couple of locks, so maybe > the return value solution is easiest. > We've also just seen another issue where multiple calls to cti_disable_hw() can cause enable_req_count to go negative. I'm going to work on a few fixes (including yours) to make sure that it's complete and post it shortly. James
On 1/5/2023 9:55 PM, James Clark wrote: > > On 04/01/2023 13:11, James Clark wrote: >> >> On 24/12/2022 14:17, Mao Jinlong wrote: >>> In commit 6746eae4bbad ("coresight: cti: Fix hang in cti_disable_hw()") >>> PM runtime calls are removed from cti_enable_hw/cti_disable_hw. When >>> enabling CTI by writing enable sysfs node, clock for accessing CTI >>> register won't be enabled. Device will crash due to register access >>> issue. Add PM runtime call in enable_store to fix this issue. >>> >>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> >>> --- >>> drivers/hwtracing/coresight/coresight-cti-sysfs.c | 11 +++++++++-- >>> 1 file changed, 9 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c >>> index 6d59c815ecf5..b1ed424ae043 100644 >>> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c >>> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c >>> @@ -108,10 +108,17 @@ static ssize_t enable_store(struct device *dev, >>> if (ret) >>> return ret; >>> >>> - if (val) >>> + if (val) { >>> + ret = pm_runtime_resume_and_get(dev->parent); >>> + if (ret) >>> + return ret; >>> ret = cti_enable(drvdata->csdev); >>> - else >>> + if (ret) >>> + pm_runtime_put(dev->parent); >>> + } else { >>> ret = cti_disable(drvdata->csdev); >>> + pm_runtime_put(dev->parent); >> Hi Jinlong, >> >> This new pm_runtime_put() causes this when writing 0 to enable: >> >> [ 483.253814] coresight-cti 23020000.cti: Runtime PM usage count >> underflow! >> >> Maybe we can modify cti_disable_hw() to return a value to indicate that >> the disable actually happened, and only then call pm_runtime_put(). >> >> I suppose you could also check in the store function if it was already >> enabled first, but then I don't know what kind of locking that would >> need? cti_disable_hw() already seems to have a couple of locks, so maybe >> the return value solution is easiest. >> > We've also just seen another issue where multiple calls to > cti_disable_hw() can cause enable_req_count to go negative. I'm going to > work on a few fixes (including yours) to make sure that it's complete > and post it shortly. Ok, Thank you, James. > > James
diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 6d59c815ecf5..b1ed424ae043 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -108,10 +108,17 @@ static ssize_t enable_store(struct device *dev, if (ret) return ret; - if (val) + if (val) { + ret = pm_runtime_resume_and_get(dev->parent); + if (ret) + return ret; ret = cti_enable(drvdata->csdev); - else + if (ret) + pm_runtime_put(dev->parent); + } else { ret = cti_disable(drvdata->csdev); + pm_runtime_put(dev->parent); + } if (ret) return ret; return size;