diff mbox series

[v3,10/11] clk: starfive: Add StarFive JH7110 always-on clock driver

Message ID 20221220005054.34518-11-hal.feng@starfivetech.com
State New
Headers
Series Basic clock and reset support for StarFive JH7110 RISC-V SoC |

Commit Message

Hal Feng Dec. 20, 2022, 12:50 a.m. UTC 
  From: Emil Renner Berthing <kernel@esmil.dk>

Add driver for the StarFive JH7110 always-on clock controller
and register an auxiliary device for always-on reset controller
which is named as "reset-aon".

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 drivers/clk/starfive/Kconfig                  |  11 ++
 drivers/clk/starfive/Makefile                 |   1 +
 .../clk/starfive/clk-starfive-jh7110-aon.c    | 156 ++++++++++++++++++
 3 files changed, 168 insertions(+)
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c

Comments

kernel test robot Dec. 23, 2022, 11:28 a.m. UTC | #1 
Hi Hal,

I love your patch! Perhaps something to improve:

[auto build test WARNING on 830b3c68c1fb1e9176028d02ef86f3cf76aa2476]

url:    https://github.com/intel-lab-lkp/linux/commits/Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131
base:   830b3c68c1fb1e9176028d02ef86f3cf76aa2476
patch link:    https://lore.kernel.org/r/20221220005054.34518-11-hal.feng%40starfivetech.com
patch subject: [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on clock driver
config: riscv-randconfig-s042-20221218
compiler: riscv64-linux-gcc (GCC) 12.1.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/intel-lab-lkp/linux/commit/e30705645d46071dc6c7ce5485b5ebf3aeeaa59c
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131
        git checkout e30705645d46071dc6c7ce5485b5ebf3aeeaa59c
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv SHELL=/bin/bash drivers/clk/starfive/ drivers/reset/starfive/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

sparse warnings: (new ones prefixed by >>)
   WARNING: invalid argument to '-march': '_zihintpause'
>> drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@     expected void *data @@     got void [noderef] __iomem *base @@
   drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse:     expected void *data
   drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse:     got void [noderef] __iomem *base

vim +86 drivers/clk/starfive/clk-starfive-jh7110-aon.c

    67	
    68	static int jh7110_aoncrg_probe(struct platform_device *pdev)
    69	{
    70		struct jh71x0_clk_priv *priv;
    71		unsigned int idx;
    72		int ret;
    73	
    74		priv = devm_kzalloc(&pdev->dev,
    75				    struct_size(priv, reg, JH7110_AONCLK_END),
    76				    GFP_KERNEL);
    77		if (!priv)
    78			return -ENOMEM;
    79	
    80		spin_lock_init(&priv->rmw_lock);
    81		priv->dev = &pdev->dev;
    82		priv->base = devm_platform_ioremap_resource(pdev, 0);
    83		if (IS_ERR(priv->base))
    84			return PTR_ERR(priv->base);
    85	
  > 86		dev_set_drvdata(priv->dev, priv->base);
    87	
    88		for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
    89			u32 max = jh7110_aonclk_data[idx].max;
    90			struct clk_parent_data parents[4] = {};
    91			struct clk_init_data init = {
    92				.name = jh7110_aonclk_data[idx].name,
    93				.ops = starfive_jh71x0_clk_ops(max),
    94				.parent_data = parents,
    95				.num_parents =
    96					((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
    97				.flags = jh7110_aonclk_data[idx].flags,
    98			};
    99			struct jh71x0_clk *clk = &priv->reg[idx];
   100			unsigned int i;
   101	
   102			for (i = 0; i < init.num_parents; i++) {
   103				unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
   104	
   105				if (pidx < JH7110_AONCLK_END)
   106					parents[i].hw = &priv->reg[pidx].hw;
   107				else if (pidx == JH7110_AONCLK_OSC)
   108					parents[i].fw_name = "osc";
   109				else if (pidx == JH7110_AONCLK_RTC_OSC)
   110					parents[i].fw_name = "rtc_osc";
   111				else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
   112					parents[i].fw_name = "gmac0_rmii_refin";
   113				else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
   114					parents[i].fw_name = "gmac0_rgmii_rxin";
   115				else if (pidx == JH7110_AONCLK_STG_AXIAHB)
   116					parents[i].fw_name = "stg_axiahb";
   117				else if (pidx == JH7110_AONCLK_APB_BUS)
   118					parents[i].fw_name = "apb_bus";
   119				else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
   120					parents[i].fw_name = "gmac0_gtxclk";
   121			}
   122	
   123			clk->hw.init = &init;
   124			clk->idx = idx;
   125			clk->max_div = max & JH71X0_CLK_DIV_MASK;
   126	
   127			ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
   128			if (ret)
   129				return ret;
   130		}
   131	
   132		ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
   133		if (ret)
   134			return ret;
   135	
   136		return jh7110_reset_controller_register(priv, "reset-aon", 1);
   137	}
   138
kernel test robot Jan. 5, 2023, 1:44 p.m. UTC | #2 
Hi Hal,

I love your patch! Perhaps something to improve:

[auto build test WARNING on 830b3c68c1fb1e9176028d02ef86f3cf76aa2476]

url:    https://github.com/intel-lab-lkp/linux/commits/Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131
base:   830b3c68c1fb1e9176028d02ef86f3cf76aa2476
patch link:    https://lore.kernel.org/r/20221220005054.34518-11-hal.feng%40starfivetech.com
patch subject: [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on clock driver
config: riscv-randconfig-s042-20230105
compiler: riscv64-linux-gcc (GCC) 12.1.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/intel-lab-lkp/linux/commit/e30705645d46071dc6c7ce5485b5ebf3aeeaa59c
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131
        git checkout e30705645d46071dc6c7ce5485b5ebf3aeeaa59c
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv SHELL=/bin/bash drivers/clk/starfive/ drivers/reset/starfive/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

sparse warnings: (new ones prefixed by >>)
   WARNING: invalid argument to '-march': '_zihintpause'
>> drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@     expected void *data @@     got void [noderef] __iomem *base @@
   drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse:     expected void *data
   drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse:     got void [noderef] __iomem *base

vim +86 drivers/clk/starfive/clk-starfive-jh7110-aon.c

    67	
    68	static int jh7110_aoncrg_probe(struct platform_device *pdev)
    69	{
    70		struct jh71x0_clk_priv *priv;
    71		unsigned int idx;
    72		int ret;
    73	
    74		priv = devm_kzalloc(&pdev->dev,
    75				    struct_size(priv, reg, JH7110_AONCLK_END),
    76				    GFP_KERNEL);
    77		if (!priv)
    78			return -ENOMEM;
    79	
    80		spin_lock_init(&priv->rmw_lock);
    81		priv->dev = &pdev->dev;
    82		priv->base = devm_platform_ioremap_resource(pdev, 0);
    83		if (IS_ERR(priv->base))
    84			return PTR_ERR(priv->base);
    85	
  > 86		dev_set_drvdata(priv->dev, priv->base);
    87	
    88		for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
    89			u32 max = jh7110_aonclk_data[idx].max;
    90			struct clk_parent_data parents[4] = {};
    91			struct clk_init_data init = {
    92				.name = jh7110_aonclk_data[idx].name,
    93				.ops = starfive_jh71x0_clk_ops(max),
    94				.parent_data = parents,
    95				.num_parents =
    96					((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
    97				.flags = jh7110_aonclk_data[idx].flags,
    98			};
    99			struct jh71x0_clk *clk = &priv->reg[idx];
   100			unsigned int i;
   101	
   102			for (i = 0; i < init.num_parents; i++) {
   103				unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
   104	
   105				if (pidx < JH7110_AONCLK_END)
   106					parents[i].hw = &priv->reg[pidx].hw;
   107				else if (pidx == JH7110_AONCLK_OSC)
   108					parents[i].fw_name = "osc";
   109				else if (pidx == JH7110_AONCLK_RTC_OSC)
   110					parents[i].fw_name = "rtc_osc";
   111				else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
   112					parents[i].fw_name = "gmac0_rmii_refin";
   113				else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
   114					parents[i].fw_name = "gmac0_rgmii_rxin";
   115				else if (pidx == JH7110_AONCLK_STG_AXIAHB)
   116					parents[i].fw_name = "stg_axiahb";
   117				else if (pidx == JH7110_AONCLK_APB_BUS)
   118					parents[i].fw_name = "apb_bus";
   119				else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
   120					parents[i].fw_name = "gmac0_gtxclk";
   121			}
   122	
   123			clk->hw.init = &init;
   124			clk->idx = idx;
   125			clk->max_div = max & JH71X0_CLK_DIV_MASK;
   126	
   127			ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
   128			if (ret)
   129				return ret;
   130		}
   131	
   132		ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
   133		if (ret)
   134			return ret;
   135	
   136		return jh7110_reset_controller_register(priv, "reset-aon", 1);
   137	}
   138
diff mbox series

Patch

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 4640d0665d1c..2aa664f2cdee 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -31,3 +31,14 @@  config CLK_STARFIVE_JH7110_SYS
 	help
 	  Say yes here to support the system clock controller on the
 	  StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_AON
+	tristate "StarFive JH7110 always-on clock support"
+	depends on CLK_STARFIVE_JH7110_SYS
+	select AUXILIARY_BUS
+	select CLK_STARFIVE_JH71X0
+	select RESET_STARFIVE_JH7110
+	default CLK_STARFIVE_JH7110_SYS
+	help
+	  Say yes here to support the always-on clock controller on the
+	  StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 5ca4e887fb9c..f3df7d957b1e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -5,3 +5,4 @@  obj-$(CONFIG_CLK_STARFIVE_JH7100)	+= clk-starfive-jh7100.o
 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)	+= clk-starfive-jh7100-audio.o
 
 obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS)	+= clk-starfive-jh7110-sys.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_AON)	+= clk-starfive-jh7110-aon.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
new file mode 100644
index 000000000000..75a0f6e64f15
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -0,0 +1,156 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Always-On Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh71x0.h"
+
+/* external clocks */
+#define JH7110_AONCLK_OSC		(JH7110_AONCLK_END + 0)
+#define JH7110_AONCLK_RTC_OSC		(JH7110_AONCLK_END + 1)
+#define JH7110_AONCLK_GMAC0_RMII_REFIN	(JH7110_AONCLK_END + 2)
+#define JH7110_AONCLK_GMAC0_RGMII_RXIN	(JH7110_AONCLK_END + 3)
+#define JH7110_AONCLK_STG_AXIAHB	(JH7110_AONCLK_END + 4)
+#define JH7110_AONCLK_APB_BUS		(JH7110_AONCLK_END + 5)
+#define JH7110_AONCLK_GMAC0_GTXCLK	(JH7110_AONCLK_END + 6)
+
+static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
+	/* source */
+	JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
+	JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
+		    JH7110_AONCLK_OSC_DIV4,
+		    JH7110_AONCLK_OSC),
+	/* gmac0 */
+	JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
+	JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
+	JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
+		    JH7110_AONCLK_GMAC0_RMII_REFIN),
+	JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", 0, 2,
+		    JH7110_AONCLK_GMAC0_GTXCLK,
+		    JH7110_AONCLK_GMAC0_RMII_RTX),
+	JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
+	JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
+		    JH7110_AONCLK_GMAC0_RGMII_RXIN,
+		    JH7110_AONCLK_GMAC0_RMII_RTX),
+	JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
+	/* otpc */
+	JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
+	/* rtc */
+	JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
+	JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
+	JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
+		    JH7110_AONCLK_RTC_OSC,
+		    JH7110_AONCLK_RTC_INTERNAL),
+	JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
+};
+
+static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct jh71x0_clk_priv *priv = data;
+	unsigned int idx = clkspec->args[0];
+
+	if (idx < JH7110_AONCLK_END)
+		return &priv->reg[idx].hw;
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_aoncrg_probe(struct platform_device *pdev)
+{
+	struct jh71x0_clk_priv *priv;
+	unsigned int idx;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev,
+			    struct_size(priv, reg, JH7110_AONCLK_END),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	spin_lock_init(&priv->rmw_lock);
+	priv->dev = &pdev->dev;
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	dev_set_drvdata(priv->dev, priv->base);
+
+	for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
+		u32 max = jh7110_aonclk_data[idx].max;
+		struct clk_parent_data parents[4] = {};
+		struct clk_init_data init = {
+			.name = jh7110_aonclk_data[idx].name,
+			.ops = starfive_jh71x0_clk_ops(max),
+			.parent_data = parents,
+			.num_parents =
+				((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+			.flags = jh7110_aonclk_data[idx].flags,
+		};
+		struct jh71x0_clk *clk = &priv->reg[idx];
+		unsigned int i;
+
+		for (i = 0; i < init.num_parents; i++) {
+			unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
+
+			if (pidx < JH7110_AONCLK_END)
+				parents[i].hw = &priv->reg[pidx].hw;
+			else if (pidx == JH7110_AONCLK_OSC)
+				parents[i].fw_name = "osc";
+			else if (pidx == JH7110_AONCLK_RTC_OSC)
+				parents[i].fw_name = "rtc_osc";
+			else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
+				parents[i].fw_name = "gmac0_rmii_refin";
+			else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
+				parents[i].fw_name = "gmac0_rgmii_rxin";
+			else if (pidx == JH7110_AONCLK_STG_AXIAHB)
+				parents[i].fw_name = "stg_axiahb";
+			else if (pidx == JH7110_AONCLK_APB_BUS)
+				parents[i].fw_name = "apb_bus";
+			else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
+				parents[i].fw_name = "gmac0_gtxclk";
+		}
+
+		clk->hw.init = &init;
+		clk->idx = idx;
+		clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+		if (ret)
+			return ret;
+	}
+
+	ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
+	if (ret)
+		return ret;
+
+	return jh7110_reset_controller_register(priv, "reset-aon", 1);
+}
+
+static const struct of_device_id jh7110_aoncrg_match[] = {
+	{ .compatible = "starfive,jh7110-aoncrg" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
+
+static struct platform_driver jh7110_aoncrg_driver = {
+	.probe = jh7110_aoncrg_probe,
+	.driver = {
+		.name = "clk-starfive-jh7110-aon",
+		.of_match_table = jh7110_aoncrg_match,
+	},
+};
+module_platform_driver(jh7110_aoncrg_driver);
+
+MODULE_AUTHOR("Emil Renner Berthing");
+MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
+MODULE_LICENSE("GPL");