Message ID | 20221019071631.15191-1-farbere@amazon.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r73-20020a632b4c000000b0045f0795c39esi17947943pgr.578.2022.10.19.00.18.29; Wed, 19 Oct 2022 00:18:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.com header.s=amazon201209 header.b=WWOtKI3Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229930AbiJSHQt (ORCPT <rfc822;samuel.l.nystrom@gmail.com> + 99 others); Wed, 19 Oct 2022 03:16:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbiJSHQp (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 19 Oct 2022 03:16:45 -0400 Received: from smtp-fw-2101.amazon.com (smtp-fw-2101.amazon.com [72.21.196.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC7CD63F01 for <linux-kernel@vger.kernel.org>; Wed, 19 Oct 2022 00:16:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1666163804; x=1697699804; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=idRMXOV7LEiNt8pIiLFFF8p2b7BGPUnm0JzpG6j/u38=; b=WWOtKI3Z4TQbu3if8eOoc9tzxA/RtaHwPVu/NIHRsBKK1J1xY8DYETIX x1Q7JmD6Vap55eZnk3vlsJHEgO7oGB5/EFPFXwF9NR0foqWPzWZ9+ORve ev9wJ1oXweZCrMx9zYz/VQDHoO//y/tHkEwwAZds+jSPQqTH8lycZodTF k=; X-IronPort-AV: E=Sophos;i="5.95,195,1661817600"; d="scan'208";a="253551215" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-pdx-2b-d803d33a.us-west-2.amazon.com) ([10.43.8.6]) by smtp-border-fw-2101.iad2.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 07:16:38 +0000 Received: from EX13MTAUWB001.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan3.pdx.amazon.com [10.236.137.198]) by email-inbound-relay-pdx-2b-d803d33a.us-west-2.amazon.com (Postfix) with ESMTPS id 9013A817ED; Wed, 19 Oct 2022 07:16:37 +0000 (UTC) Received: from EX19D013UWA002.ant.amazon.com (10.13.138.210) by EX13MTAUWB001.ant.amazon.com (10.43.161.207) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Oct 2022 07:16:33 +0000 Received: from EX13MTAUEB002.ant.amazon.com (10.43.60.12) by EX19D013UWA002.ant.amazon.com (10.13.138.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1118.15; Wed, 19 Oct 2022 07:16:33 +0000 Received: from dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com (172.19.116.181) by mail-relay.amazon.com (10.43.60.234) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 19 Oct 2022 07:16:32 +0000 Received: by dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com (Postfix, from userid 14301484) id 5D9EB2634; Wed, 19 Oct 2022 07:16:31 +0000 (UTC) From: Eliav Farber <farbere@amazon.com> To: <tudor.ambarus@microchip.com>, <pratyush@kernel.org>, <michael@walle.cc>, <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org> CC: <talel@amazon.com>, <jonnyc@amazon.com>, <hhhawa@amazon.com>, <hanochu@amazon.com>, <farbere@amazon.com>, <itamark@amazon.com>, <shellykz@amazon.com>, <amitlavi@amazon.com>, <dkl@amazon.com> Subject: [PATCH v2 1/1] mtd: spi-nor: micron-st: Enable locking for n25q256ax1/mt25qu256a Date: Wed, 19 Oct 2022 07:16:31 +0000 Message-ID: <20221019071631.15191-1-farbere@amazon.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747099500494729362?= X-GMAIL-MSGID: =?utf-8?q?1747099500494729362?= |
Series |
[v2,1/1] mtd: spi-nor: micron-st: Enable locking for n25q256ax1/mt25qu256a
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Commit Message
Farber, Eliav
Oct. 19, 2022, 7:16 a.m. UTC
n25q256ax1 [1] and mt25qu256a [2] (both have same jedec_id - 0x20bb19)
use the 4 bit Block Protection scheme and support Top/Bottom protection
via the BP and TB bits of the Status Register.
BP3 is located in bit 6 of the Status Register.
Tested on both n25q256ax1 and mt25qu256a.
[1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
[2] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf
Signed-off-by: Eliav Farber <farbere@amazon.com>
---
xxd -p /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
53464450060101ff00060110300000ff84000102800000ffffffffffffff
ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b
273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e
03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff
ffffffffffffffffffe7ffff21dcffff
md5sum /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
5ea738216f68c9f98987bb3725699a32 /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
cat /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id
20bb19104400
cat /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname
mt25qu256a
cat /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer
st
v2 --> v1:
- Enable locking also for mt25qu256a.
- Dump the SFDP tables.
drivers/mtd/spi-nor/micron-st.c | 4 ++++
1 file changed, 4 insertions(+)
Comments
Hi, Am 2022-10-19 09:16, schrieb Eliav Farber: > n25q256ax1 [1] and mt25qu256a [2] (both have same jedec_id - 0x20bb19) > use the 4 bit Block Protection scheme and support Top/Bottom protection > via the BP and TB bits of the Status Register. > BP3 is located in bit 6 of the Status Register. > Tested on both n25q256ax1 and mt25qu256a. > > [1] > https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf > [2] > https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf If you respin, you can use a "Link:" tag for the URL above. > Signed-off-by: Eliav Farber <farbere@amazon.com> > --- > xxd -p > /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp > 53464450060101ff00060110300000ff84000102800000ffffffffffffff > ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b > 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e > 03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff > ffffffffffffffffffe7ffff21dcffff > > md5sum > /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp > 5ea738216f68c9f98987bb3725699a32 > /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp > > cat > /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id > 20bb19104400 > > cat > /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname > mt25qu256a > > cat > /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer > st That's the mt25qu256a SFDP. What about the n25q256ax1? Thanks! -michael > > v2 --> v1: > - Enable locking also for mt25qu256a. > - Dump the SFDP tables. > > drivers/mtd/spi-nor/micron-st.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/mtd/spi-nor/micron-st.c > b/drivers/mtd/spi-nor/micron-st.c > index 3c9681a3f7a3..f4d0153a5b1b 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -201,11 +201,15 @@ static const struct flash_info st_nor_parts[] = { > MFR_FLAGS(USE_FSR) > }, > { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512) > + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | > + SPI_NOR_BP3_SR_BIT6) > NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) > FIXUP_FLAGS(SPI_NOR_4B_OPCODES) > MFR_FLAGS(USE_FSR) > }, > { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512) > + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | > + SPI_NOR_BP3_SR_BIT6) > NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) > MFR_FLAGS(USE_FSR) > },
On 10/19/2022 11:21 AM, Michael Walle wrote: > Hi, > > Am 2022-10-19 09:16, schrieb Eliav Farber: >> n25q256ax1 [1] and mt25qu256a [2] (both have same jedec_id - 0x20bb19) >> use the 4 bit Block Protection scheme and support Top/Bottom protection >> via the BP and TB bits of the Status Register. >> BP3 is located in bit 6 of the Status Register. >> Tested on both n25q256ax1 and mt25qu256a. >> >> [1] >> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf >> >> [2] >> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf >> > > If you respin, you can use a "Link:" tag for the URL above. Ack. >> Signed-off-by: Eliav Farber <farbere@amazon.com> >> --- >> xxd -p >> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >> >> 53464450060101ff00060110300000ff84000102800000ffffffffffffff >> ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b >> 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e >> 03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff >> ffffffffffffffffffe7ffff21dcffff >> >> md5sum >> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >> >> 5ea738216f68c9f98987bb3725699a32 >> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >> >> >> cat >> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id >> >> 20bb19104400 >> >> cat >> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname >> >> mt25qu256a >> >> cat >> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer >> >> st > > That's the mt25qu256a SFDP. What about the n25q256ax1? On the same card, with same NOR flash memory I'm running two different kernel versions. First version is quite old - 4.19.239 which does not support mt25qu256a and therefore device is detected as n25q256ax1. Second version is 6.1.0-rc1 and it detects the same device as mt25qu256a. So I was able to dump SFDP when running version 6.1.0-rc1, but not when running 4.19.239 which does not support the sysfs to dump the SFPD information. I checked that locking works with my changes when running on both kernel versions. -- Regards, Eliav
Am 2022-10-19 11:25, schrieb Farber, Eliav: > On 10/19/2022 11:21 AM, Michael Walle wrote: >> Hi, >> >> Am 2022-10-19 09:16, schrieb Eliav Farber: >>> n25q256ax1 [1] and mt25qu256a [2] (both have same jedec_id - >>> 0x20bb19) >>> use the 4 bit Block Protection scheme and support Top/Bottom >>> protection >>> via the BP and TB bits of the Status Register. >>> BP3 is located in bit 6 of the Status Register. >>> Tested on both n25q256ax1 and mt25qu256a. >>> >>> [1] >>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf >>> [2] >>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf >> >> If you respin, you can use a "Link:" tag for the URL above. > > Ack. > >>> Signed-off-by: Eliav Farber <farbere@amazon.com> >>> --- >>> xxd -p >>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>> 53464450060101ff00060110300000ff84000102800000ffffffffffffff >>> ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b >>> 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e >>> 03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff >>> ffffffffffffffffffe7ffff21dcffff >>> >>> md5sum >>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>> 5ea738216f68c9f98987bb3725699a32 >>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>> cat >>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id >>> 20bb19104400 >>> >>> cat >>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname >>> mt25qu256a >>> >>> cat >>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer >>> st >> >> That's the mt25qu256a SFDP. What about the n25q256ax1? > > On the same card, with same NOR flash memory I'm running two different > kernel versions. > First version is quite old - 4.19.239 which does not support mt25qu256a > and therefore device is detected as n25q256ax1. > Second version is 6.1.0-rc1 and it detects the same device as > mt25qu256a. > So I was able to dump SFDP when running version 6.1.0-rc1, but not when > running 4.19.239 which does not support the sysfs to dump the SFPD > information. > I checked that locking works with my changes when running on both > kernel > versions. So you've only tested on an mt25qu256a, correct? Then you should only add the locking to this flash device. (and maybe backport the mt25qu256a to your older kernel). -michael
On 10/19/2022 12:38 PM, Michael Walle wrote: > Am 2022-10-19 11:25, schrieb Farber, Eliav: >> On 10/19/2022 11:21 AM, Michael Walle wrote: >>> Hi, >>> >>> Am 2022-10-19 09:16, schrieb Eliav Farber: >>>> n25q256ax1 [1] and mt25qu256a [2] (both have same jedec_id - >>>> 0x20bb19) >>>> use the 4 bit Block Protection scheme and support Top/Bottom >>>> protection >>>> via the BP and TB bits of the Status Register. >>>> BP3 is located in bit 6 of the Status Register. >>>> Tested on both n25q256ax1 and mt25qu256a. >>>> >>>> [1] >>>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf >>>> >>>> [2] >>>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf >>>> >>> >>> If you respin, you can use a "Link:" tag for the URL above. >> >> Ack. >> >>>> Signed-off-by: Eliav Farber <farbere@amazon.com> >>>> --- >>>> xxd -p >>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>> >>>> 53464450060101ff00060110300000ff84000102800000ffffffffffffff >>>> ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b >>>> 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e >>>> 03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff >>>> ffffffffffffffffffe7ffff21dcffff >>>> >>>> md5sum >>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>> >>>> 5ea738216f68c9f98987bb3725699a32 >>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>> >>>> cat >>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id >>>> >>>> 20bb19104400 >>>> >>>> cat >>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname >>>> >>>> mt25qu256a >>>> >>>> cat >>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer >>>> >>>> st >>> >>> That's the mt25qu256a SFDP. What about the n25q256ax1? >> >> On the same card, with same NOR flash memory I'm running two different >> kernel versions. >> First version is quite old - 4.19.239 which does not support mt25qu256a >> and therefore device is detected as n25q256ax1. >> Second version is 6.1.0-rc1 and it detects the same device as >> mt25qu256a. >> So I was able to dump SFDP when running version 6.1.0-rc1, but not when >> running 4.19.239 which does not support the sysfs to dump the SFPD >> information. >> I checked that locking works with my changes when running on both >> kernel >> versions. > > So you've only tested on an mt25qu256a, correct? Then you should only > add the locking to this flash device. (and maybe backport the mt25qu256a > to your older kernel). I dumped SFDP tables only for mt25qu256a, but as I mentioned I tested locking functionality for both (on 4.19.239 which detects the device as n25q256ax1 and on 6.1.0-rc1 which detects the device as mt25qu256a). This is the flow I used for testing the change on both versions: # flash_lock -i /dev/mtd0 fDevice: /dev/mtd0 Start: 0 lLen: 0x1000000 Lock status: unlocked Return code: 0 # flash_lock -l /dev/mtd0 # flash_lock -i /dev/mtd0 fDevice: /dev/mtd0 Start: 0 Len: 0x1000000 Lock status: locked Return code: 1 # flash_lock -u /dev/mtd0 # flash_lock -i /dev/mtd0 Device: /dev/mtd0 Start: 0 Len: 0x1000000 Lock status: unlocked Do you still want this patch to change only mt25qu256a? -- Regards, Eliav
Am 2022-10-19 11:52, schrieb Farber, Eliav: > On 10/19/2022 12:38 PM, Michael Walle wrote: >> Am 2022-10-19 11:25, schrieb Farber, Eliav: >>> On 10/19/2022 11:21 AM, Michael Walle wrote: >>>> Hi, >>>> >>>> Am 2022-10-19 09:16, schrieb Eliav Farber: >>>>> n25q256ax1 [1] and mt25qu256a [2] (both have same jedec_id - >>>>> 0x20bb19) >>>>> use the 4 bit Block Protection scheme and support Top/Bottom >>>>> protection >>>>> via the BP and TB bits of the Status Register. >>>>> BP3 is located in bit 6 of the Status Register. >>>>> Tested on both n25q256ax1 and mt25qu256a. >>>>> >>>>> [1] >>>>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf >>>>> [2] >>>>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf >>>> >>>> If you respin, you can use a "Link:" tag for the URL above. >>> >>> Ack. >>> >>>>> Signed-off-by: Eliav Farber <farbere@amazon.com> >>>>> --- >>>>> xxd -p >>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>>> 53464450060101ff00060110300000ff84000102800000ffffffffffffff >>>>> ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b >>>>> 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e >>>>> 03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff >>>>> ffffffffffffffffffe7ffff21dcffff >>>>> >>>>> md5sum >>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>>> 5ea738216f68c9f98987bb3725699a32 >>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>>> cat >>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id >>>>> 20bb19104400 >>>>> >>>>> cat >>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname >>>>> mt25qu256a >>>>> >>>>> cat >>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer >>>>> st >>>> >>>> That's the mt25qu256a SFDP. What about the n25q256ax1? >>> >>> On the same card, with same NOR flash memory I'm running two >>> different >>> kernel versions. >>> First version is quite old - 4.19.239 which does not support >>> mt25qu256a >>> and therefore device is detected as n25q256ax1. >>> Second version is 6.1.0-rc1 and it detects the same device as >>> mt25qu256a. >>> So I was able to dump SFDP when running version 6.1.0-rc1, but not >>> when >>> running 4.19.239 which does not support the sysfs to dump the SFPD >>> information. >>> I checked that locking works with my changes when running on both >>> kernel >>> versions. >> >> So you've only tested on an mt25qu256a, correct? Then you should only >> add the locking to this flash device. (and maybe backport the >> mt25qu256a >> to your older kernel). > > I dumped SFDP tables only for mt25qu256a, but as I mentioned I tested > locking functionality for both (on 4.19.239 which detects the device as > n25q256ax1 and on 6.1.0-rc1 which detects the device as mt25qu256a). > This is the flow I used for testing the change on both versions: You said you've tested on the same board, thus it has the same flash device. But with the older kernel it was detected as a different part. So the question is, what is the correct part number? I.e. what is the _actual_ flash device soldered on your board? -michael
On 10/19/2022 1:23 PM, Michael Walle wrote: > Am 2022-10-19 11:52, schrieb Farber, Eliav: >> On 10/19/2022 12:38 PM, Michael Walle wrote: >>> Am 2022-10-19 11:25, schrieb Farber, Eliav: >>>> On 10/19/2022 11:21 AM, Michael Walle wrote: >>>>> Hi, >>>>> >>>>> Am 2022-10-19 09:16, schrieb Eliav Farber: >>>>>> n25q256ax1 [1] and mt25qu256a [2] (both have same jedec_id - >>>>>> 0x20bb19) >>>>>> use the 4 bit Block Protection scheme and support Top/Bottom >>>>>> protection >>>>>> via the BP and TB bits of the Status Register. >>>>>> BP3 is located in bit 6 of the Status Register. >>>>>> Tested on both n25q256ax1 and mt25qu256a. >>>>>> >>>>>> [1] >>>>>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf >>>>>> >>>>>> [2] >>>>>> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf >>>>>> >>>>> >>>>> If you respin, you can use a "Link:" tag for the URL above. >>>> >>>> Ack. >>>> >>>>>> Signed-off-by: Eliav Farber <farbere@amazon.com> >>>>>> --- >>>>>> xxd -p >>>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>>>> >>>>>> 53464450060101ff00060110300000ff84000102800000ffffffffffffff >>>>>> ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b >>>>>> 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e >>>>>> 03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff >>>>>> ffffffffffffffffffe7ffff21dcffff >>>>>> >>>>>> md5sum >>>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>>>> >>>>>> 5ea738216f68c9f98987bb3725699a32 >>>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp >>>>>> >>>>>> cat >>>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id >>>>>> >>>>>> 20bb19104400 >>>>>> >>>>>> cat >>>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname >>>>>> >>>>>> mt25qu256a >>>>>> >>>>>> cat >>>>>> /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer >>>>>> >>>>>> st >>>>> >>>>> That's the mt25qu256a SFDP. What about the n25q256ax1? >>>> >>>> On the same card, with same NOR flash memory I'm running two >>>> different >>>> kernel versions. >>>> First version is quite old - 4.19.239 which does not support >>>> mt25qu256a >>>> and therefore device is detected as n25q256ax1. >>>> Second version is 6.1.0-rc1 and it detects the same device as >>>> mt25qu256a. >>>> So I was able to dump SFDP when running version 6.1.0-rc1, but not >>>> when >>>> running 4.19.239 which does not support the sysfs to dump the SFPD >>>> information. >>>> I checked that locking works with my changes when running on both >>>> kernel >>>> versions. >>> >>> So you've only tested on an mt25qu256a, correct? Then you should only >>> add the locking to this flash device. (and maybe backport the >>> mt25qu256a >>> to your older kernel). >> >> I dumped SFDP tables only for mt25qu256a, but as I mentioned I tested >> locking functionality for both (on 4.19.239 which detects the device as >> n25q256ax1 and on 6.1.0-rc1 which detects the device as mt25qu256a). >> This is the flow I used for testing the change on both versions: > > You said you've tested on the same board, thus it has the same flash > device. But with the older kernel it was detected as a different part. > > So the question is, what is the correct part number? I.e. what is the > _actual_ flash device soldered on your board? I have found out that we use MT25QU256ABA8ESF-0SIT so I'll release a patch for mt25qu256a only. -- Thanks, Eliav
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 3c9681a3f7a3..f4d0153a5b1b 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -201,11 +201,15 @@ static const struct flash_info st_nor_parts[] = { MFR_FLAGS(USE_FSR) }, { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512) + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | + SPI_NOR_BP3_SR_BIT6) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) MFR_FLAGS(USE_FSR) }, { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512) + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | + SPI_NOR_BP3_SR_BIT6) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) MFR_FLAGS(USE_FSR) },