diff mbox series

[4/5] gpio: Add support for Renesas RZ/V2M PWC

Message ID 20221213224310.543243-5-fabrizio.castro.jz@renesas.com
State New
Headers
Series Driver support for RZ/V2M PWC |

Commit Message

Fabrizio Castro Dec. 13, 2022, 10:43 p.m. UTC 
  The RZ/V2M SoC contains an External Power Sequence Controller (PWC)
module. This module provides an external power supply on/off sequence,
on/off signal for the LPDDR4 core power supply, control signals for
external I/O power supplies of the SD host interfaces, and key input
signals.
PWC is essentially a Multi-Function Device (MFD).

The driver just implements the control signals for external I/O
power supplies of the SD host interfaces as gpios, and it relies on
syscon and simple-mfd.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 drivers/gpio/Kconfig          |   8 +++
 drivers/gpio/Makefile         |   1 +
 drivers/gpio/gpio-rzv2m-pwc.c | 123 ++++++++++++++++++++++++++++++++++
 3 files changed, 132 insertions(+)
 create mode 100644 drivers/gpio/gpio-rzv2m-pwc.c

Comments

Bartosz Golaszewski Jan. 2, 2023, 12:50 p.m. UTC | #1 
On Tue, Dec 13, 2022 at 11:43 PM Fabrizio Castro
<fabrizio.castro.jz@renesas.com> wrote:
>
> The RZ/V2M SoC contains an External Power Sequence Controller (PWC)
> module. This module provides an external power supply on/off sequence,
> on/off signal for the LPDDR4 core power supply, control signals for
> external I/O power supplies of the SD host interfaces, and key input
> signals.
> PWC is essentially a Multi-Function Device (MFD).
>
> The driver just implements the control signals for external I/O
> power supplies of the SD host interfaces as gpios, and it relies on
> syscon and simple-mfd.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
>  drivers/gpio/Kconfig          |   8 +++
>  drivers/gpio/Makefile         |   1 +
>  drivers/gpio/gpio-rzv2m-pwc.c | 123 ++++++++++++++++++++++++++++++++++
>  3 files changed, 132 insertions(+)
>  create mode 100644 drivers/gpio/gpio-rzv2m-pwc.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index e6ebc4c90a5d..e016919b9643 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -553,6 +553,14 @@ config GPIO_ROCKCHIP
>         help
>           Say yes here to support GPIO on Rockchip SoCs.
>
> +config GPIO_RZV2M_PWC
> +       tristate "Renesas RZ/V2M PWC GPIO support"
> +       depends on MFD_SYSCON
> +       depends on ARCH_R9A09G011 || COMPILE_TEST
> +       help
> +         Say yes here to support the External Power Sequence Controller (PWC)
> +         GPIO controller driver for RZ/V2M devices.
> +
>  config GPIO_SAMA5D2_PIOBU
>         tristate "SAMA5D2 PIOBU GPIO support"
>         depends on MFD_SYSCON
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 3462a138764a..5f655684603f 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -132,6 +132,7 @@ obj-$(CONFIG_GPIO_RDC321X)          += gpio-rdc321x.o
>  obj-$(CONFIG_GPIO_REALTEK_OTTO)                += gpio-realtek-otto.o
>  obj-$(CONFIG_GPIO_REG)                 += gpio-reg.o
>  obj-$(CONFIG_GPIO_ROCKCHIP)    += gpio-rockchip.o
> +obj-$(CONFIG_GPIO_RZV2M_PWC)           += gpio-rzv2m-pwc.o
>  obj-$(CONFIG_ARCH_SA1100)              += gpio-sa1100.o
>  obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)       += gpio-sama5d2-piobu.o
>  obj-$(CONFIG_GPIO_SCH311X)             += gpio-sch311x.o
> diff --git a/drivers/gpio/gpio-rzv2m-pwc.c b/drivers/gpio/gpio-rzv2m-pwc.c
> new file mode 100644
> index 000000000000..672d868cb8c9
> --- /dev/null
> +++ b/drivers/gpio/gpio-rzv2m-pwc.c
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + *
> + * GPIO driver for Renesas RZ/V2M External Power Sequence Controller (PWC)
> + */
> +
> +#include <linux/gpio/driver.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/spinlock.h>
> +
> +struct rzv2m_pwc_gpio_priv {
> +       struct gpio_chip gp;
> +       int offset;
> +       struct regmap *regmap;
> +       DECLARE_BITMAP(ch_en_bits, 2);
> +};
> +
> +static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset,
> +                              int value)
> +{
> +       struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip);
> +       u32 reg;
> +
> +       /* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */
> +       reg = BIT(offset + 16);
> +       if (value)
> +               reg |= BIT(offset);
> +
> +       regmap_write(priv->regmap, priv->offset, reg);
> +
> +       if (value)
> +               set_bit(offset, priv->ch_en_bits);
> +       else
> +               clear_bit(offset, priv->ch_en_bits);

You can use assign_bit() here and pass value to it.

> +}
> +
> +static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset)
> +{
> +       struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip);
> +
> +       return test_bit(offset, priv->ch_en_bits);
> +}
> +
> +static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc,
> +                                          unsigned int nr, int value)
> +{
> +       if (nr > 1)
> +               return -EINVAL;
> +
> +       rzv2m_pwc_gpio_set(gc, nr, value);
> +
> +       return 0;
> +}
> +
> +static const struct gpio_chip rzv2m_pwc_gc = {
> +       .label = "rzv2m_pwc_gpio",
> +       .owner = THIS_MODULE,
> +       .get = rzv2m_pwc_gpio_get,
> +       .set = rzv2m_pwc_gpio_set,
> +       .direction_output = rzv2m_pwc_gpio_direction_output,
> +       .can_sleep = false,
> +       .ngpio = 2,
> +       .base = -1,
> +};
> +
> +static int rzv2m_pwc_gpio_probe(struct platform_device *pdev)
> +{
> +       struct rzv2m_pwc_gpio_priv *priv;
> +       int err;
> +
> +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +                                                      "regmap");
> +
> +       if (IS_ERR(priv->regmap))
> +               return dev_err_probe(&pdev->dev, PTR_ERR(priv->regmap),
> +                                    "Can't find regmap property");
> +
> +       err = of_property_read_u32(pdev->dev.of_node, "offset", &priv->offset);

Please don't use OF APIs in drivers anymore, use
device_property_read_u32() instead.

Otherwise looks pretty good!

Bart

> +       if (err)
> +               return dev_err_probe(&pdev->dev, -EINVAL,
> +                                    "Can't find offset property");
> +
> +       /*
> +        * The register used by this driver cannot be read, therefore set the
> +        * outputs to their default values and initialize priv->ch_en_bits accordingly.
> +        * BIT 16 enables write to BIT 0, BIT 17 enables write to BIT 1, and the
> +        * default value of both BIT 0 and BIT 1 is 0.
> +        */
> +       regmap_write(priv->regmap, priv->offset, BIT(17) | BIT(16));
> +       bitmap_zero(priv->ch_en_bits, 2);
> +
> +       priv->gp = rzv2m_pwc_gc;
> +       priv->gp.parent = pdev->dev.parent;
> +       priv->gp.fwnode = dev_fwnode(&pdev->dev);
> +
> +       return devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv);
> +}
> +
> +static const struct of_device_id rzv2m_pwc_gpio_of_match[] = {
> +       { .compatible = "renesas,rzv2m-pwc-gpio" },
> +       { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, rzv2m_pwc_gpio_of_match);
> +
> +static struct platform_driver rzv2m_pwc_gpio_driver = {
> +       .probe = rzv2m_pwc_gpio_probe,
> +       .driver = {
> +               .name = "rzv2m_pwc_gpio",
> +               .of_match_table = of_match_ptr(rzv2m_pwc_gpio_of_match),
> +       },
> +};
> +module_platform_driver(rzv2m_pwc_gpio_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>");
> +MODULE_DESCRIPTION("Renesas RZ/V2M PWC GPIO");
> --
> 2.34.1
>
Fabrizio Castro Jan. 5, 2023, 5:40 p.m. UTC | #2 
Hi Bartosz,

Thanks for your feedback!

> 
> On Tue, Dec 13, 2022 at 11:43 PM Fabrizio Castro
> <fabrizio.castro.jz@renesas.com> wrote:
> >
> > The RZ/V2M SoC contains an External Power Sequence Controller (PWC)
> > module. This module provides an external power supply on/off sequence,
> > on/off signal for the LPDDR4 core power supply, control signals for
> > external I/O power supplies of the SD host interfaces, and key input
> > signals.
> > PWC is essentially a Multi-Function Device (MFD).
> >
> > The driver just implements the control signals for external I/O
> > power supplies of the SD host interfaces as gpios, and it relies on
> > syscon and simple-mfd.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > ---
> >  drivers/gpio/Kconfig          |   8 +++
> >  drivers/gpio/Makefile         |   1 +
> >  drivers/gpio/gpio-rzv2m-pwc.c | 123 ++++++++++++++++++++++++++++++++++
> >  3 files changed, 132 insertions(+)
> >  create mode 100644 drivers/gpio/gpio-rzv2m-pwc.c
> >
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index e6ebc4c90a5d..e016919b9643 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -553,6 +553,14 @@ config GPIO_ROCKCHIP
> >         help
> >           Say yes here to support GPIO on Rockchip SoCs.
> >
> > +config GPIO_RZV2M_PWC
> > +       tristate "Renesas RZ/V2M PWC GPIO support"
> > +       depends on MFD_SYSCON
> > +       depends on ARCH_R9A09G011 || COMPILE_TEST
> > +       help
> > +         Say yes here to support the External Power Sequence Controller
> (PWC)
> > +         GPIO controller driver for RZ/V2M devices.
> > +
> >  config GPIO_SAMA5D2_PIOBU
> >         tristate "SAMA5D2 PIOBU GPIO support"
> >         depends on MFD_SYSCON
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> > index 3462a138764a..5f655684603f 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -132,6 +132,7 @@ obj-$(CONFIG_GPIO_RDC321X)          += gpio-
> rdc321x.o
> >  obj-$(CONFIG_GPIO_REALTEK_OTTO)                += gpio-realtek-otto.o
> >  obj-$(CONFIG_GPIO_REG)                 += gpio-reg.o
> >  obj-$(CONFIG_GPIO_ROCKCHIP)    += gpio-rockchip.o
> > +obj-$(CONFIG_GPIO_RZV2M_PWC)           += gpio-rzv2m-pwc.o
> >  obj-$(CONFIG_ARCH_SA1100)              += gpio-sa1100.o
> >  obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)       += gpio-sama5d2-piobu.o
> >  obj-$(CONFIG_GPIO_SCH311X)             += gpio-sch311x.o
> > diff --git a/drivers/gpio/gpio-rzv2m-pwc.c b/drivers/gpio/gpio-rzv2m-
> pwc.c
> > new file mode 100644
> > index 000000000000..672d868cb8c9
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-rzv2m-pwc.c
> > @@ -0,0 +1,123 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2022 Renesas Electronics Corporation
> > + *
> > + * GPIO driver for Renesas RZ/V2M External Power Sequence Controller
> (PWC)
> > + */
> > +
> > +#include <linux/gpio/driver.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/spinlock.h>
> > +
> > +struct rzv2m_pwc_gpio_priv {
> > +       struct gpio_chip gp;
> > +       int offset;
> > +       struct regmap *regmap;
> > +       DECLARE_BITMAP(ch_en_bits, 2);
> > +};
> > +
> > +static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int
> offset,
> > +                              int value)
> > +{
> > +       struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip);
> > +       u32 reg;
> > +
> > +       /* BIT 16 enables write to BIT 0, and BIT 17 enables write to
> BIT 1 */
> > +       reg = BIT(offset + 16);
> > +       if (value)
> > +               reg |= BIT(offset);
> > +
> > +       regmap_write(priv->regmap, priv->offset, reg);
> > +
> > +       if (value)
> > +               set_bit(offset, priv->ch_en_bits);
> > +       else
> > +               clear_bit(offset, priv->ch_en_bits);
> 
> You can use assign_bit() here and pass value to it.

Good point, I will fix it in v3.

> 
> > +}
> > +
> > +static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int
> offset)
> > +{
> > +       struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip);
> > +
> > +       return test_bit(offset, priv->ch_en_bits);
> > +}
> > +
> > +static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc,
> > +                                          unsigned int nr, int value)
> > +{
> > +       if (nr > 1)
> > +               return -EINVAL;
> > +
> > +       rzv2m_pwc_gpio_set(gc, nr, value);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct gpio_chip rzv2m_pwc_gc = {
> > +       .label = "rzv2m_pwc_gpio",
> > +       .owner = THIS_MODULE,
> > +       .get = rzv2m_pwc_gpio_get,
> > +       .set = rzv2m_pwc_gpio_set,
> > +       .direction_output = rzv2m_pwc_gpio_direction_output,
> > +       .can_sleep = false,
> > +       .ngpio = 2,
> > +       .base = -1,
> > +};
> > +
> > +static int rzv2m_pwc_gpio_probe(struct platform_device *pdev)
> > +{
> > +       struct rzv2m_pwc_gpio_priv *priv;
> > +       int err;
> > +
> > +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       priv->regmap = syscon_regmap_lookup_by_phandle(pdev-
> >dev.of_node,
> > +                                                      "regmap");
> > +
> > +       if (IS_ERR(priv->regmap))
> > +               return dev_err_probe(&pdev->dev, PTR_ERR(priv->regmap),
> > +                                    "Can't find regmap property");
> > +
> > +       err = of_property_read_u32(pdev->dev.of_node, "offset", &priv-
> >offset);
> 
> Please don't use OF APIs in drivers anymore, use
> device_property_read_u32() instead.


Gotcha, I'll fix it in v3.

Thanks!
Fab

> 
> Otherwise looks pretty good!
> 
> Bart
> 
> > +       if (err)
> > +               return dev_err_probe(&pdev->dev, -EINVAL,
> > +                                    "Can't find offset property");
> > +
> > +       /*
> > +        * The register used by this driver cannot be read, therefore
> set the
> > +        * outputs to their default values and initialize priv-
> >ch_en_bits accordingly.
> > +        * BIT 16 enables write to BIT 0, BIT 17 enables write to BIT 1,
> and the
> > +        * default value of both BIT 0 and BIT 1 is 0.
> > +        */
> > +       regmap_write(priv->regmap, priv->offset, BIT(17) | BIT(16));
> > +       bitmap_zero(priv->ch_en_bits, 2);
> > +
> > +       priv->gp = rzv2m_pwc_gc;
> > +       priv->gp.parent = pdev->dev.parent;
> > +       priv->gp.fwnode = dev_fwnode(&pdev->dev);
> > +
> > +       return devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv);
> > +}
> > +
> > +static const struct of_device_id rzv2m_pwc_gpio_of_match[] = {
> > +       { .compatible = "renesas,rzv2m-pwc-gpio" },
> > +       { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, rzv2m_pwc_gpio_of_match);
> > +
> > +static struct platform_driver rzv2m_pwc_gpio_driver = {
> > +       .probe = rzv2m_pwc_gpio_probe,
> > +       .driver = {
> > +               .name = "rzv2m_pwc_gpio",
> > +               .of_match_table = of_match_ptr(rzv2m_pwc_gpio_of_match),
> > +       },
> > +};
> > +module_platform_driver(rzv2m_pwc_gpio_driver);
> > +
> > +MODULE_LICENSE("GPL");
> > +MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>");
> > +MODULE_DESCRIPTION("Renesas RZ/V2M PWC GPIO");
> > --
> > 2.34.1
> >
diff mbox series

Patch

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e6ebc4c90a5d..e016919b9643 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -553,6 +553,14 @@  config GPIO_ROCKCHIP
 	help
 	  Say yes here to support GPIO on Rockchip SoCs.
 
+config GPIO_RZV2M_PWC
+	tristate "Renesas RZ/V2M PWC GPIO support"
+	depends on MFD_SYSCON
+	depends on ARCH_R9A09G011 || COMPILE_TEST
+	help
+	  Say yes here to support the External Power Sequence Controller (PWC)
+	  GPIO controller driver for RZ/V2M devices.
+
 config GPIO_SAMA5D2_PIOBU
 	tristate "SAMA5D2 PIOBU GPIO support"
 	depends on MFD_SYSCON
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3462a138764a..5f655684603f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -132,6 +132,7 @@  obj-$(CONFIG_GPIO_RDC321X)		+= gpio-rdc321x.o
 obj-$(CONFIG_GPIO_REALTEK_OTTO)		+= gpio-realtek-otto.o
 obj-$(CONFIG_GPIO_REG)			+= gpio-reg.o
 obj-$(CONFIG_GPIO_ROCKCHIP)	+= gpio-rockchip.o
+obj-$(CONFIG_GPIO_RZV2M_PWC)		+= gpio-rzv2m-pwc.o
 obj-$(CONFIG_ARCH_SA1100)		+= gpio-sa1100.o
 obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)	+= gpio-sama5d2-piobu.o
 obj-$(CONFIG_GPIO_SCH311X)		+= gpio-sch311x.o
diff --git a/drivers/gpio/gpio-rzv2m-pwc.c b/drivers/gpio/gpio-rzv2m-pwc.c
new file mode 100644
index 000000000000..672d868cb8c9
--- /dev/null
+++ b/drivers/gpio/gpio-rzv2m-pwc.c
@@ -0,0 +1,123 @@ 
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * GPIO driver for Renesas RZ/V2M External Power Sequence Controller (PWC)
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/spinlock.h>
+
+struct rzv2m_pwc_gpio_priv {
+	struct gpio_chip gp;
+	int offset;
+	struct regmap *regmap;
+	DECLARE_BITMAP(ch_en_bits, 2);
+};
+
+static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset,
+			       int value)
+{
+	struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip);
+	u32 reg;
+
+	/* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */
+	reg = BIT(offset + 16);
+	if (value)
+		reg |= BIT(offset);
+
+	regmap_write(priv->regmap, priv->offset, reg);
+
+	if (value)
+		set_bit(offset, priv->ch_en_bits);
+	else
+		clear_bit(offset, priv->ch_en_bits);
+}
+
+static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+	struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip);
+
+	return test_bit(offset, priv->ch_en_bits);
+}
+
+static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc,
+					   unsigned int nr, int value)
+{
+	if (nr > 1)
+		return -EINVAL;
+
+	rzv2m_pwc_gpio_set(gc, nr, value);
+
+	return 0;
+}
+
+static const struct gpio_chip rzv2m_pwc_gc = {
+	.label = "rzv2m_pwc_gpio",
+	.owner = THIS_MODULE,
+	.get = rzv2m_pwc_gpio_get,
+	.set = rzv2m_pwc_gpio_set,
+	.direction_output = rzv2m_pwc_gpio_direction_output,
+	.can_sleep = false,
+	.ngpio = 2,
+	.base = -1,
+};
+
+static int rzv2m_pwc_gpio_probe(struct platform_device *pdev)
+{
+	struct rzv2m_pwc_gpio_priv *priv;
+	int err;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+						       "regmap");
+
+	if (IS_ERR(priv->regmap))
+		return dev_err_probe(&pdev->dev, PTR_ERR(priv->regmap),
+				     "Can't find regmap property");
+
+	err = of_property_read_u32(pdev->dev.of_node, "offset", &priv->offset);
+	if (err)
+		return dev_err_probe(&pdev->dev, -EINVAL,
+				     "Can't find offset property");
+
+	/*
+	 * The register used by this driver cannot be read, therefore set the
+	 * outputs to their default values and initialize priv->ch_en_bits accordingly.
+	 * BIT 16 enables write to BIT 0, BIT 17 enables write to BIT 1, and the
+	 * default value of both BIT 0 and BIT 1 is 0.
+	 */
+	regmap_write(priv->regmap, priv->offset, BIT(17) | BIT(16));
+	bitmap_zero(priv->ch_en_bits, 2);
+
+	priv->gp = rzv2m_pwc_gc;
+	priv->gp.parent = pdev->dev.parent;
+	priv->gp.fwnode = dev_fwnode(&pdev->dev);
+
+	return devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv);
+}
+
+static const struct of_device_id rzv2m_pwc_gpio_of_match[] = {
+	{ .compatible = "renesas,rzv2m-pwc-gpio" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzv2m_pwc_gpio_of_match);
+
+static struct platform_driver rzv2m_pwc_gpio_driver = {
+	.probe = rzv2m_pwc_gpio_probe,
+	.driver = {
+		.name = "rzv2m_pwc_gpio",
+		.of_match_table = of_match_ptr(rzv2m_pwc_gpio_of_match),
+	},
+};
+module_platform_driver(rzv2m_pwc_gpio_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/V2M PWC GPIO");