Message ID | 20221229101846.981223-1-konrad.dybcio@linaro.org |
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State | New |
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[83.9.31.184]) by smtp.gmail.com with ESMTPSA id j18-20020a056512109200b00498f67cbfa9sm3028632lfg.22.2022.12.29.02.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 02:18:49 -0800 (PST) From: Konrad Dybcio <konrad.dybcio@linaro.org> To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Akhil P Oommen <quic_akhilpo@quicinc.com>, Emma Anholt <emma@anholt.net>, Jordan Crouse <jordan@cosmicpenguin.net>, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/msm/adreno: Make adreno quirks not overwrite each other Date: Thu, 29 Dec 2022 11:18:45 +0100 Message-Id: <20221229101846.981223-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753543557961614796?= X-GMAIL-MSGID: =?utf-8?q?1753543557961614796?= |
Series |
drm/msm/adreno: Make adreno quirks not overwrite each other
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Commit Message
Konrad Dybcio
Dec. 29, 2022, 10:18 a.m. UTC
So far the adreno quirks have all been assigned with an OR operator,
which is problematic, because they were assigned consecutive integer
values, which makes checking them with an AND operator kind of no bueno..
Switch to using BIT(n) so that only the quirks that the programmer chose
are taken into account when evaluating info->quirks & ADRENO_QUIRK_...
Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
Comments
On 2022-12-29 11:18:45, Konrad Dybcio wrote: > So far the adreno quirks have all been assigned with an OR operator, > which is problematic, because they were assigned consecutive integer > values, which makes checking them with an AND operator kind of no bueno.. > > Switch to using BIT(n) so that only the quirks that the programmer chose > are taken into account when evaluating info->quirks & ADRENO_QUIRK_... > > Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Nice catch! Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Not sure if it's the right Fixes commit though, as it would have worked when ADRENO_QUIRK_LMLOADKILL_DISABLE was added with constant 4 instead of 3 in 370063ee427a ("drm/msm/adreno: Add A540 support"), but then using bitflags in an enum value type is invalid anyway, AFAIK. - Marijn > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index c85857c0a228..5eb254c9832a 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -29,11 +29,9 @@ enum { > ADRENO_FW_MAX, > }; > > -enum adreno_quirks { > - ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, > - ADRENO_QUIRK_FAULT_DETECT_MASK = 2, > - ADRENO_QUIRK_LMLOADKILL_DISABLE = 3, > -}; > +#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) > +#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) > +#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) > > struct adreno_rev { > uint8_t core; > @@ -65,7 +63,7 @@ struct adreno_info { > const char *name; > const char *fw[ADRENO_FW_MAX]; > uint32_t gmem; > - enum adreno_quirks quirks; > + u64 quirks; > struct msm_gpu *(*init)(struct drm_device *dev); > const char *zapfw; > u32 inactive_period; > -- > 2.39.0 >
On 29/12/2022 12:18, Konrad Dybcio wrote: > So far the adreno quirks have all been assigned with an OR operator, > which is problematic, because they were assigned consecutive integer > values, which makes checking them with an AND operator kind of no bueno.. > > Switch to using BIT(n) so that only the quirks that the programmer chose > are taken into account when evaluating info->quirks & ADRENO_QUIRK_... > > Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-)-- With best wishes Dmitry
On Thu, Dec 29, 2022 at 2:47 AM Marijn Suijten <marijn.suijten@somainline.org> wrote: > > On 2022-12-29 11:18:45, Konrad Dybcio wrote: > > So far the adreno quirks have all been assigned with an OR operator, > > which is problematic, because they were assigned consecutive integer > > values, which makes checking them with an AND operator kind of no bueno.. > > > > Switch to using BIT(n) so that only the quirks that the programmer chose > > are taken into account when evaluating info->quirks & ADRENO_QUIRK_... > > > > Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support") > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Nice catch! > > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > > Not sure if it's the right Fixes commit though, as it would have worked > when ADRENO_QUIRK_LMLOADKILL_DISABLE was added with constant 4 instead > of 3 in 370063ee427a ("drm/msm/adreno: Add A540 support"), but then > using bitflags in an enum value type is invalid anyway, AFAIK. It isn't a thing that c++ like so much, but for c code, gdb will decode enum bitfields in a sensible way (IIRC). Also, maybe it doesn't matter at this point, but it would conflict for stable backports prior to adding LMLOADKILL_DISABLE. with the fixes msg corrected, Reviewed-by: Rob Clark <robdclark@gmail.com> > - Marijn > > > --- > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > index c85857c0a228..5eb254c9832a 100644 > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > @@ -29,11 +29,9 @@ enum { > > ADRENO_FW_MAX, > > }; > > > > -enum adreno_quirks { > > - ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, > > - ADRENO_QUIRK_FAULT_DETECT_MASK = 2, > > - ADRENO_QUIRK_LMLOADKILL_DISABLE = 3, > > -}; > > +#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) > > +#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) > > +#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) > > > > struct adreno_rev { > > uint8_t core; > > @@ -65,7 +63,7 @@ struct adreno_info { > > const char *name; > > const char *fw[ADRENO_FW_MAX]; > > uint32_t gmem; > > - enum adreno_quirks quirks; > > + u64 quirks; > > struct msm_gpu *(*init)(struct drm_device *dev); > > const char *zapfw; > > u32 inactive_period; > > -- > > 2.39.0 > >
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index c85857c0a228..5eb254c9832a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -29,11 +29,9 @@ enum { ADRENO_FW_MAX, }; -enum adreno_quirks { - ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, - ADRENO_QUIRK_FAULT_DETECT_MASK = 2, - ADRENO_QUIRK_LMLOADKILL_DISABLE = 3, -}; +#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) +#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) +#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) struct adreno_rev { uint8_t core; @@ -65,7 +63,7 @@ struct adreno_info { const char *name; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; - enum adreno_quirks quirks; + u64 quirks; struct msm_gpu *(*init)(struct drm_device *dev); const char *zapfw; u32 inactive_period;