diff mbox series

[RFC,3/6] RISC-V: Add Zvkh[a,b] ISA extension support

Message ID 20221221170706.2877188-4-christoph.muellner@vrull.eu
State Accepted
Headers
Series RISC-V: Add support for vector crypto extensions |

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Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Christoph Müllner Dec. 21, 2022, 5:07 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvkh[a,b] ISA extension instructions, which are part
of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c                     | 13 +++++++++++++
 gas/testsuite/gas/riscv/zvkha.d       | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvkha_zvkhb.s |  3 +++
 gas/testsuite/gas/riscv/zvkhb.d       | 12 ++++++++++++
 include/opcode/riscv-opc.h            | 11 +++++++++++
 include/opcode/riscv.h                |  3 +++
 opcodes/riscv-opc.c                   |  5 +++++
 7 files changed, 59 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkha.d
 create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
 create mode 100644 gas/testsuite/gas/riscv/zvkhb.d

Comments

Jeff Law Dec. 21, 2022, 9:24 p.m. UTC | #1 
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> of the vector crypto extensions.
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>   bfd/elfxx-riscv.c                     | 13 +++++++++++++
>   gas/testsuite/gas/riscv/zvkha.d       | 12 ++++++++++++
>   gas/testsuite/gas/riscv/zvkha_zvkhb.s |  3 +++
>   gas/testsuite/gas/riscv/zvkhb.d       | 12 ++++++++++++
>   include/opcode/riscv-opc.h            | 11 +++++++++++
>   include/opcode/riscv.h                |  3 +++
>   opcodes/riscv-opc.c                   |  5 +++++
>   7 files changed, 59 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvkha.d
>   create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
>   create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
Looks reasonable to me.  Just one comment nit below...



> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index bb716c8c9d0..35d3e653147 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
>   /* Zvkg instructions.  */
>   {"vghmac.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
>   
> +/* Xvkh[a,b] instructions.  */
Are these X or Z?

Jeff
Christoph Müllner Dec. 22, 2022, 2:17 p.m. UTC | #2 
On Wed, Dec 21, 2022 at 10:24 PM Jeff Law <jeffreyalaw@gmail.com> wrote:

>
>
> On 12/21/22 10:07, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> > of the vector crypto extensions.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >   bfd/elfxx-riscv.c                     | 13 +++++++++++++
> >   gas/testsuite/gas/riscv/zvkha.d       | 12 ++++++++++++
> >   gas/testsuite/gas/riscv/zvkha_zvkhb.s |  3 +++
> >   gas/testsuite/gas/riscv/zvkhb.d       | 12 ++++++++++++
> >   include/opcode/riscv-opc.h            | 11 +++++++++++
> >   include/opcode/riscv.h                |  3 +++
> >   opcodes/riscv-opc.c                   |  5 +++++
> >   7 files changed, 59 insertions(+)
> >   create mode 100644 gas/testsuite/gas/riscv/zvkha.d
> >   create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
> >   create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
> Looks reasonable to me.  Just one comment nit below...
>
>
>
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index bb716c8c9d0..35d3e653147 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
> >   /* Zvkg instructions.  */
> >   {"vghmac.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV,
> MASK_VGHMACVV, match_opcode, 0},
> >
> > +/* Xvkh[a,b] instructions.  */
> Are these X or Z?
>

Thanks for spotting this!



>
> Jeff
>
Philipp Tomsich Jan. 3, 2023, 10 p.m. UTC | #3 
On Wed, 21 Dec 2022 at 18:07, Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> of the vector crypto extensions.

This should be Zvknh[ab] (the 'n' has been missing throughout the
patch: i.e., filenames, march, INSN_CLASS_*, etc.), as that's what the
specification uses.

Watch this space for a v2 of the series.

> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  bfd/elfxx-riscv.c                     | 13 +++++++++++++
>  gas/testsuite/gas/riscv/zvkha.d       | 12 ++++++++++++
>  gas/testsuite/gas/riscv/zvkha_zvkhb.s |  3 +++
>  gas/testsuite/gas/riscv/zvkhb.d       | 12 ++++++++++++
>  include/opcode/riscv-opc.h            | 11 +++++++++++
>  include/opcode/riscv.h                |  3 +++
>  opcodes/riscv-opc.c                   |  5 +++++
>  7 files changed, 59 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/zvkha.d
>  create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
>  create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 6dfae35ff0b..fad49e4176a 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1207,6 +1207,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>    {"zve64d",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvkb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvkg",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> +  {"zvkha",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> +  {"zvkhb",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvl32b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvl64b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvl128b",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> @@ -2421,6 +2423,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>        return riscv_subset_supports (rps, "zvkb");
>      case INSN_CLASS_ZVKG:
>        return riscv_subset_supports (rps, "zvkg");
> +    case INSN_CLASS_ZVKHA:
> +      return riscv_subset_supports (rps, "zvkha");
> +    case INSN_CLASS_ZVKHB:
> +      return riscv_subset_supports (rps, "zvkhb");
> +    case INSN_CLASS_ZVKHA_OR_ZVKHB:
> +      return (riscv_subset_supports (rps, "zvkha")
> +             || riscv_subset_supports (rps, "zvkhb"));
>      case INSN_CLASS_SVINVAL:
>        return riscv_subset_supports (rps, "svinval");
>      case INSN_CLASS_H:
> @@ -2583,6 +2592,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
>        return _("zvkb");
>      case INSN_CLASS_ZVKG:
>        return _("zvkg");
> +    case INSN_CLASS_ZVKHA:
> +      return _("zvkha");
> +    case INSN_CLASS_ZVKHB:
> +      return _("zvkhb");
>      case INSN_CLASS_SVINVAL:
>        return "svinval";
>      case INSN_CLASS_H:
> diff --git a/gas/testsuite/gas/riscv/zvkha.d b/gas/testsuite/gas/riscv/zvkha.d
> new file mode 100644
> index 00000000000..61d6f4e77bb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkha.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64gc_zvkha
> +#source: zvkha_zvkhb.s
> +#objdump: -dr
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +0+000 <.text>:
> +[      ]+[0-9a-f]+:[   ]+ba862277[     ]+vsha2ch.vv[   ]+v4,v8,v12
> +[      ]+[0-9a-f]+:[   ]+be862277[     ]+vsha2cl.vv[   ]+v4,v8,v12
> +[      ]+[0-9a-f]+:[   ]+b6862277[     ]+vsha2ms.vv[   ]+v4,v8,v12
> diff --git a/gas/testsuite/gas/riscv/zvkha_zvkhb.s b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
> new file mode 100644
> index 00000000000..d20e6310531
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
> @@ -0,0 +1,3 @@
> +       vsha2ch.vv v4, v8, v12
> +       vsha2cl.vv v4, v8, v12
> +       vsha2ms.vv v4, v8, v12
> diff --git a/gas/testsuite/gas/riscv/zvkhb.d b/gas/testsuite/gas/riscv/zvkhb.d
> new file mode 100644
> index 00000000000..61d0c1c4652
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkhb.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64gc_zvkhb
> +#source: zvkha_zvkhb.s
> +#objdump: -dr
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +0+000 <.text>:
> +[      ]+[0-9a-f]+:[   ]+ba862277[     ]+vsha2ch.vv[   ]+v4,v8,v12
> +[      ]+[0-9a-f]+:[   ]+be862277[     ]+vsha2cl.vv[   ]+v4,v8,v12
> +[      ]+[0-9a-f]+:[   ]+b6862277[     ]+vsha2ms.vv[   ]+v4,v8,v12
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 4daffed4d84..2d22f88acb7 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2087,6 +2087,13 @@
>  /* Zvkg instructions.  */
>  #define MATCH_VGHMACVV 0xb2002077
>  #define MASK_VGHMACVV 0xfe00707f
> +/* Zvkh[a,b] instructions.  */
> +#define MATCH_VSHA2CHVV 0xba002077
> +#define MASK_VSHA2CHVV 0xfe00707f
> +#define MATCH_VSHA2CLVV 0xbe002077
> +#define MASK_VSHA2CLVV 0xfe00707f
> +#define MATCH_VSHA2MSVV 0xb6002077
> +#define MASK_VSHA2MSVV 0xfe00707f
>  /* Svinval instruction.  */
>  #define MATCH_SINVAL_VMA 0x16000073
>  #define MASK_SINVAL_VMA 0xfe007fff
> @@ -3167,6 +3174,10 @@ DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
>  DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
>  /* Zvkg instructions.  */
>  DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV)
> +/* Zvkh[a,b] instructions.  */
> +DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
> +DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
> +DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
>  /* Vendor-specific (T-Head) XTheadBa instructions.  */
>  DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
>  /* Vendor-specific (T-Head) XTheadBb instructions.  */
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 060438a64d0..be5650297a7 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -411,6 +411,9 @@ enum riscv_insn_class
>    INSN_CLASS_ZVEF,
>    INSN_CLASS_ZVKB,
>    INSN_CLASS_ZVKG,
> +  INSN_CLASS_ZVKHA,
> +  INSN_CLASS_ZVKHB,
> +  INSN_CLASS_ZVKHA_OR_ZVKHB,
>    INSN_CLASS_SVINVAL,
>    INSN_CLASS_ZICBOM,
>    INSN_CLASS_ZICBOP,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index bb716c8c9d0..35d3e653147 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
>  /* Zvkg instructions.  */
>  {"vghmac.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
>
> +/* Xvkh[a,b] instructions.  */
> +{"vsha2ch.vv",  0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CHVV, MASK_VSHA2CHVV, match_opcode, 0},
> +{"vsha2cl.vv",  0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
> +{"vsha2ms.vv",  0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
> +
>  /* Supervisor instructions.  */
>  {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
>  {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
> --
> 2.38.1
>
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6dfae35ff0b..fad49e4176a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1207,6 +1207,8 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2421,6 +2423,13 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_ZVKG:
       return riscv_subset_supports (rps, "zvkg");
+    case INSN_CLASS_ZVKHA:
+      return riscv_subset_supports (rps, "zvkha");
+    case INSN_CLASS_ZVKHB:
+      return riscv_subset_supports (rps, "zvkhb");
+    case INSN_CLASS_ZVKHA_OR_ZVKHB:
+      return (riscv_subset_supports (rps, "zvkha")
+	      || riscv_subset_supports (rps, "zvkhb"));
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2583,6 +2592,10 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvkb");
     case INSN_CLASS_ZVKG:
       return _("zvkg");
+    case INSN_CLASS_ZVKHA:
+      return _("zvkha");
+    case INSN_CLASS_ZVKHB:
+      return _("zvkhb");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkha.d b/gas/testsuite/gas/riscv/zvkha.d
new file mode 100644
index 00000000000..61d6f4e77bb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkha.d
@@ -0,0 +1,12 @@ 
+#as: -march=rv64gc_zvkha
+#source: zvkha_zvkhb.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+be862277[ 	]+vsha2cl.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+b6862277[ 	]+vsha2ms.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvkha_zvkhb.s b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
new file mode 100644
index 00000000000..d20e6310531
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
@@ -0,0 +1,3 @@ 
+	vsha2ch.vv v4, v8, v12
+	vsha2cl.vv v4, v8, v12
+	vsha2ms.vv v4, v8, v12
diff --git a/gas/testsuite/gas/riscv/zvkhb.d b/gas/testsuite/gas/riscv/zvkhb.d
new file mode 100644
index 00000000000..61d0c1c4652
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkhb.d
@@ -0,0 +1,12 @@ 
+#as: -march=rv64gc_zvkhb
+#source: zvkha_zvkhb.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+be862277[ 	]+vsha2cl.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+b6862277[ 	]+vsha2ms.vv[ 	]+v4,v8,v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 4daffed4d84..2d22f88acb7 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2087,6 +2087,13 @@ 
 /* Zvkg instructions.  */
 #define MATCH_VGHMACVV 0xb2002077
 #define MASK_VGHMACVV 0xfe00707f
+/* Zvkh[a,b] instructions.  */
+#define MATCH_VSHA2CHVV 0xba002077
+#define MASK_VSHA2CHVV 0xfe00707f
+#define MATCH_VSHA2CLVV 0xbe002077
+#define MASK_VSHA2CLVV 0xfe00707f
+#define MATCH_VSHA2MSVV 0xb6002077
+#define MASK_VSHA2MSVV 0xfe00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3167,6 +3174,10 @@  DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
 DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
 /* Zvkg instructions.  */
 DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV)
+/* Zvkh[a,b] instructions.  */
+DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
+DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
+DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 060438a64d0..be5650297a7 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -411,6 +411,9 @@  enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
+  INSN_CLASS_ZVKHA,
+  INSN_CLASS_ZVKHB,
+  INSN_CLASS_ZVKHA_OR_ZVKHB,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bb716c8c9d0..35d3e653147 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1834,6 +1834,11 @@  const struct riscv_opcode riscv_opcodes[] =
 /* Zvkg instructions.  */
 {"vghmac.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
 
+/* Xvkh[a,b] instructions.  */
+{"vsha2ch.vv",  0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CHVV, MASK_VSHA2CHVV, match_opcode, 0},
+{"vsha2cl.vv",  0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
+{"vsha2ms.vv",  0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },