Message ID | 20221219191427.480085-3-manivannan.sadhasivam@linaro.org |
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State | New |
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Series |
Qcom: Add GIC-ITS support to SM8450 PCIe controllers
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Commit Message
Manivannan Sadhasivam
Dec. 19, 2022, 7:14 p.m. UTC
The Qcom PCIe controller is capable of using either internal MSI controller
or the external GIC-ITS for receiving the MSIs from endpoint devices.
Currently, the binding only documents the internal MSI implementation.
Let's document the GIC-ITS imeplementation by making use of msi-map and
msi-map-mask properties.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
Comments
On 19/12/2022 20:14, Manivannan Sadhasivam wrote: > The Qcom PCIe controller is capable of using either internal MSI controller > or the external GIC-ITS for receiving the MSIs from endpoint devices. > Currently, the binding only documents the internal MSI implementation. > > Let's document the GIC-ITS imeplementation by making use of msi-map and > msi-map-mask properties. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 02450fb26bb9..24c3e7ef14eb 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -100,18 +100,28 @@ properties: > description: GPIO controlled connection to WAKE# signal > maxItems: 1 > > + msi-map: true > + > + msi-map-mask: true You should not need these. Just like interrup-map-mask, it is coming from pci-bus.yaml. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 02450fb26bb9..24c3e7ef14eb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -100,18 +100,28 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + msi-map: true + + msi-map-mask: true + required: - compatible - reg - reg-names - - interrupts - - interrupt-names - - "#interrupt-cells" - interrupt-map-mask - interrupt-map - clocks - clock-names +oneOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + allOf: - $ref: /schemas/pci/pci-bus.yaml# - if: