diff mbox series

[v1,2/9] media: verisilicon: Add AV1 decoder mode and controls

Message ID 20221219155616.848690-3-benjamin.gaignard@collabora.com
State New
Headers
Series AV1 stateless decoder for RK3588 |

Commit Message

Benjamin Gaignard Dec. 19, 2022, 3:56 p.m. UTC 
  Add AV1 decoder as new decoder mode to Hantro driver.
Register needed AV1 controls for the decoder.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
 drivers/media/platform/verisilicon/hantro.h   |  3 +++
 .../media/platform/verisilicon/hantro_drv.c   | 21 +++++++++++++++++++
 2 files changed, 24 insertions(+)

Comments

kernel test robot Dec. 19, 2022, 6:25 p.m. UTC | #1 
Hi Benjamin,

I love your patch! Yet something to improve:

[auto build test ERROR on media-tree/master]
[also build test ERROR on rockchip/for-next linus/master v6.1 next-20221219]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Benjamin-Gaignard/AV1-stateless-decoder-for-RK3588/20221220-000013
base:   git://linuxtv.org/media_tree.git master
patch link:    https://lore.kernel.org/r/20221219155616.848690-3-benjamin.gaignard%40collabora.com
patch subject: [PATCH v1 2/9] media: verisilicon: Add AV1 decoder mode and controls
config: m68k-allmodconfig
compiler: m68k-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/d60040964a6a110a1d3a9af3794c27e25a24182d
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Benjamin-Gaignard/AV1-stateless-decoder-for-RK3588/20221220-000013
        git checkout d60040964a6a110a1d3a9af3794c27e25a24182d
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/media/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/media/platform/verisilicon/hantro_drv.c:504:31: error: 'V4L2_CID_STATELESS_AV1_FRAME' undeclared here (not in a function); did you mean 'V4L2_CID_STATELESS_VP9_FRAME'?
     504 |                         .id = V4L2_CID_STATELESS_AV1_FRAME,
         |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
         |                               V4L2_CID_STATELESS_VP9_FRAME
>> drivers/media/platform/verisilicon/hantro_drv.c:509:31: error: 'V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY' undeclared here (not in a function)
     509 |                         .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
         |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/media/platform/verisilicon/hantro_drv.c:510:35: error: 'V4L2_AV1_MAX_TILE_COUNT' undeclared here (not in a function)
     510 |                         .dims = { V4L2_AV1_MAX_TILE_COUNT },
         |                                   ^~~~~~~~~~~~~~~~~~~~~~~
>> drivers/media/platform/verisilicon/hantro_drv.c:515:31: error: 'V4L2_CID_STATELESS_AV1_SEQUENCE' undeclared here (not in a function); did you mean 'V4L2_CID_STATELESS_MPEG2_SEQUENCE'?
     515 |                         .id = V4L2_CID_STATELESS_AV1_SEQUENCE,
         |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         |                               V4L2_CID_STATELESS_MPEG2_SEQUENCE
>> drivers/media/platform/verisilicon/hantro_drv.c:520:31: error: 'V4L2_CID_STATELESS_AV1_FILM_GRAIN' undeclared here (not in a function); did you mean 'V4L2_CID_STATELESS_VP9_FRAME'?
     520 |                         .id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
         |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         |                               V4L2_CID_STATELESS_VP9_FRAME


vim +504 drivers/media/platform/verisilicon/hantro_drv.c

   338	
   339	#define HANTRO_JPEG_ACTIVE_MARKERS	(V4L2_JPEG_ACTIVE_MARKER_APP0 | \
   340						 V4L2_JPEG_ACTIVE_MARKER_COM | \
   341						 V4L2_JPEG_ACTIVE_MARKER_DQT | \
   342						 V4L2_JPEG_ACTIVE_MARKER_DHT)
   343	
   344	static const struct hantro_ctrl controls[] = {
   345		{
   346			.codec = HANTRO_JPEG_ENCODER,
   347			.cfg = {
   348				.id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
   349				.min = 5,
   350				.max = 100,
   351				.step = 1,
   352				.def = 50,
   353				.ops = &hantro_jpeg_ctrl_ops,
   354			},
   355		}, {
   356			.codec = HANTRO_JPEG_ENCODER,
   357			.cfg = {
   358				.id = V4L2_CID_JPEG_ACTIVE_MARKER,
   359				.max = HANTRO_JPEG_ACTIVE_MARKERS,
   360				.def = HANTRO_JPEG_ACTIVE_MARKERS,
   361				/*
   362				 * Changing the set of active markers/segments also
   363				 * messes up the alignment of the JPEG header, which
   364				 * is needed to allow the hardware to write directly
   365				 * to the output buffer. Implementing this introduces
   366				 * a lot of complexity for little gain, as the markers
   367				 * enabled is already the minimum required set.
   368				 */
   369				.flags = V4L2_CTRL_FLAG_READ_ONLY,
   370			},
   371		}, {
   372			.codec = HANTRO_MPEG2_DECODER,
   373			.cfg = {
   374				.id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
   375			},
   376		}, {
   377			.codec = HANTRO_MPEG2_DECODER,
   378			.cfg = {
   379				.id = V4L2_CID_STATELESS_MPEG2_PICTURE,
   380			},
   381		}, {
   382			.codec = HANTRO_MPEG2_DECODER,
   383			.cfg = {
   384				.id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
   385			},
   386		}, {
   387			.codec = HANTRO_VP8_DECODER,
   388			.cfg = {
   389				.id = V4L2_CID_STATELESS_VP8_FRAME,
   390			},
   391		}, {
   392			.codec = HANTRO_H264_DECODER,
   393			.cfg = {
   394				.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
   395			},
   396		}, {
   397			.codec = HANTRO_H264_DECODER,
   398			.cfg = {
   399				.id = V4L2_CID_STATELESS_H264_SPS,
   400				.ops = &hantro_ctrl_ops,
   401			},
   402		}, {
   403			.codec = HANTRO_H264_DECODER,
   404			.cfg = {
   405				.id = V4L2_CID_STATELESS_H264_PPS,
   406			},
   407		}, {
   408			.codec = HANTRO_H264_DECODER,
   409			.cfg = {
   410				.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
   411			},
   412		}, {
   413			.codec = HANTRO_H264_DECODER,
   414			.cfg = {
   415				.id = V4L2_CID_STATELESS_H264_DECODE_MODE,
   416				.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
   417				.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
   418				.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
   419			},
   420		}, {
   421			.codec = HANTRO_H264_DECODER,
   422			.cfg = {
   423				.id = V4L2_CID_STATELESS_H264_START_CODE,
   424				.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
   425				.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
   426				.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
   427			},
   428		}, {
   429			.codec = HANTRO_H264_DECODER,
   430			.cfg = {
   431				.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
   432				.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
   433				.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
   434				.menu_skip_mask =
   435				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
   436				.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
   437			}
   438		}, {
   439			.codec = HANTRO_HEVC_DECODER,
   440			.cfg = {
   441				.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
   442				.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
   443				.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
   444				.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
   445			},
   446		}, {
   447			.codec = HANTRO_HEVC_DECODER,
   448			.cfg = {
   449				.id = V4L2_CID_STATELESS_HEVC_START_CODE,
   450				.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
   451				.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
   452				.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
   453			},
   454		}, {
   455			.codec = HANTRO_HEVC_DECODER,
   456			.cfg = {
   457				.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
   458				.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
   459				.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
   460				.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
   461			},
   462		}, {
   463			.codec = HANTRO_HEVC_DECODER,
   464			.cfg = {
   465				.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
   466				.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
   467				.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
   468			},
   469		}, {
   470			.codec = HANTRO_HEVC_DECODER,
   471			.cfg = {
   472				.id = V4L2_CID_STATELESS_HEVC_SPS,
   473				.ops = &hantro_ctrl_ops,
   474			},
   475		}, {
   476			.codec = HANTRO_HEVC_DECODER,
   477			.cfg = {
   478				.id = V4L2_CID_STATELESS_HEVC_PPS,
   479			},
   480		}, {
   481			.codec = HANTRO_HEVC_DECODER,
   482			.cfg = {
   483				.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
   484			},
   485		}, {
   486			.codec = HANTRO_HEVC_DECODER,
   487			.cfg = {
   488				.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
   489			},
   490		}, {
   491			.codec = HANTRO_VP9_DECODER,
   492			.cfg = {
   493				.id = V4L2_CID_STATELESS_VP9_FRAME,
   494				.ops = &hantro_vp9_ctrl_ops,
   495			},
   496		}, {
   497			.codec = HANTRO_VP9_DECODER,
   498			.cfg = {
   499				.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
   500			},
   501		}, {
   502			.codec = HANTRO_AV1_DECODER,
   503			.cfg = {
 > 504				.id = V4L2_CID_STATELESS_AV1_FRAME,
   505			},
   506		}, {
   507			.codec = HANTRO_AV1_DECODER,
   508			.cfg = {
 > 509				.id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
 > 510				.dims = { V4L2_AV1_MAX_TILE_COUNT },
   511			},
   512		}, {
   513			.codec = HANTRO_AV1_DECODER,
   514			.cfg = {
 > 515				.id = V4L2_CID_STATELESS_AV1_SEQUENCE,
   516			},
   517		}, {
   518			.codec = HANTRO_AV1_DECODER,
   519			.cfg = {
 > 520				.id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
   521			},
   522		},
   523	};
   524
Nicolas Dufresne Dec. 19, 2022, 8:26 p.m. UTC | #2 
Le mardi 20 décembre 2022 à 02:25 +0800, kernel test robot a écrit :
> Hi Benjamin,
> 
> I love your patch! Yet something to improve:

This is expected as kernel next does not pull the uAPI v3 for this CODEC. The
patchset is RFC I believe, we will have to send a non-rfc one before this test
can pass.

> 
> [auto build test ERROR on media-tree/master]
> [also build test ERROR on rockchip/for-next linus/master v6.1 next-20221219]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
> 
> url:    https://github.com/intel-lab-lkp/linux/commits/Benjamin-Gaignard/AV1-stateless-decoder-for-RK3588/20221220-000013
> base:   git://linuxtv.org/media_tree.git master
> patch link:    https://lore.kernel.org/r/20221219155616.848690-3-benjamin.gaignard%40collabora.com
> patch subject: [PATCH v1 2/9] media: verisilicon: Add AV1 decoder mode and controls
> config: m68k-allmodconfig
> compiler: m68k-linux-gcc (GCC) 12.1.0
> reproduce (this is a W=1 build):
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # https://github.com/intel-lab-lkp/linux/commit/d60040964a6a110a1d3a9af3794c27e25a24182d
>         git remote add linux-review https://github.com/intel-lab-lkp/linux
>         git fetch --no-tags linux-review Benjamin-Gaignard/AV1-stateless-decoder-for-RK3588/20221220-000013
>         git checkout d60040964a6a110a1d3a9af3794c27e25a24182d
>         # save the config file
>         mkdir build_dir && cp config build_dir/.config
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k olddefconfig
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/media/
> 
> If you fix the issue, kindly add following tag where applicable
> > Reported-by: kernel test robot <lkp@intel.com>
> 
> All errors (new ones prefixed by >>):
> 
> > > drivers/media/platform/verisilicon/hantro_drv.c:504:31: error: 'V4L2_CID_STATELESS_AV1_FRAME' undeclared here (not in a function); did you mean 'V4L2_CID_STATELESS_VP9_FRAME'?
>      504 |                         .id = V4L2_CID_STATELESS_AV1_FRAME,
>          |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>          |                               V4L2_CID_STATELESS_VP9_FRAME
> > > drivers/media/platform/verisilicon/hantro_drv.c:509:31: error: 'V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY' undeclared here (not in a function)
>      509 |                         .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
>          |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > drivers/media/platform/verisilicon/hantro_drv.c:510:35: error: 'V4L2_AV1_MAX_TILE_COUNT' undeclared here (not in a function)
>      510 |                         .dims = { V4L2_AV1_MAX_TILE_COUNT },
>          |                                   ^~~~~~~~~~~~~~~~~~~~~~~
> > > drivers/media/platform/verisilicon/hantro_drv.c:515:31: error: 'V4L2_CID_STATELESS_AV1_SEQUENCE' undeclared here (not in a function); did you mean 'V4L2_CID_STATELESS_MPEG2_SEQUENCE'?
>      515 |                         .id = V4L2_CID_STATELESS_AV1_SEQUENCE,
>          |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>          |                               V4L2_CID_STATELESS_MPEG2_SEQUENCE
> > > drivers/media/platform/verisilicon/hantro_drv.c:520:31: error: 'V4L2_CID_STATELESS_AV1_FILM_GRAIN' undeclared here (not in a function); did you mean 'V4L2_CID_STATELESS_VP9_FRAME'?
>      520 |                         .id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
>          |                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>          |                               V4L2_CID_STATELESS_VP9_FRAME
> 
> 
> vim +504 drivers/media/platform/verisilicon/hantro_drv.c
> 
>    338	
>    339	#define HANTRO_JPEG_ACTIVE_MARKERS	(V4L2_JPEG_ACTIVE_MARKER_APP0 | \
>    340						 V4L2_JPEG_ACTIVE_MARKER_COM | \
>    341						 V4L2_JPEG_ACTIVE_MARKER_DQT | \
>    342						 V4L2_JPEG_ACTIVE_MARKER_DHT)
>    343	
>    344	static const struct hantro_ctrl controls[] = {
>    345		{
>    346			.codec = HANTRO_JPEG_ENCODER,
>    347			.cfg = {
>    348				.id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
>    349				.min = 5,
>    350				.max = 100,
>    351				.step = 1,
>    352				.def = 50,
>    353				.ops = &hantro_jpeg_ctrl_ops,
>    354			},
>    355		}, {
>    356			.codec = HANTRO_JPEG_ENCODER,
>    357			.cfg = {
>    358				.id = V4L2_CID_JPEG_ACTIVE_MARKER,
>    359				.max = HANTRO_JPEG_ACTIVE_MARKERS,
>    360				.def = HANTRO_JPEG_ACTIVE_MARKERS,
>    361				/*
>    362				 * Changing the set of active markers/segments also
>    363				 * messes up the alignment of the JPEG header, which
>    364				 * is needed to allow the hardware to write directly
>    365				 * to the output buffer. Implementing this introduces
>    366				 * a lot of complexity for little gain, as the markers
>    367				 * enabled is already the minimum required set.
>    368				 */
>    369				.flags = V4L2_CTRL_FLAG_READ_ONLY,
>    370			},
>    371		}, {
>    372			.codec = HANTRO_MPEG2_DECODER,
>    373			.cfg = {
>    374				.id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
>    375			},
>    376		}, {
>    377			.codec = HANTRO_MPEG2_DECODER,
>    378			.cfg = {
>    379				.id = V4L2_CID_STATELESS_MPEG2_PICTURE,
>    380			},
>    381		}, {
>    382			.codec = HANTRO_MPEG2_DECODER,
>    383			.cfg = {
>    384				.id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
>    385			},
>    386		}, {
>    387			.codec = HANTRO_VP8_DECODER,
>    388			.cfg = {
>    389				.id = V4L2_CID_STATELESS_VP8_FRAME,
>    390			},
>    391		}, {
>    392			.codec = HANTRO_H264_DECODER,
>    393			.cfg = {
>    394				.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
>    395			},
>    396		}, {
>    397			.codec = HANTRO_H264_DECODER,
>    398			.cfg = {
>    399				.id = V4L2_CID_STATELESS_H264_SPS,
>    400				.ops = &hantro_ctrl_ops,
>    401			},
>    402		}, {
>    403			.codec = HANTRO_H264_DECODER,
>    404			.cfg = {
>    405				.id = V4L2_CID_STATELESS_H264_PPS,
>    406			},
>    407		}, {
>    408			.codec = HANTRO_H264_DECODER,
>    409			.cfg = {
>    410				.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
>    411			},
>    412		}, {
>    413			.codec = HANTRO_H264_DECODER,
>    414			.cfg = {
>    415				.id = V4L2_CID_STATELESS_H264_DECODE_MODE,
>    416				.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
>    417				.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
>    418				.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
>    419			},
>    420		}, {
>    421			.codec = HANTRO_H264_DECODER,
>    422			.cfg = {
>    423				.id = V4L2_CID_STATELESS_H264_START_CODE,
>    424				.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
>    425				.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
>    426				.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
>    427			},
>    428		}, {
>    429			.codec = HANTRO_H264_DECODER,
>    430			.cfg = {
>    431				.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
>    432				.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
>    433				.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
>    434				.menu_skip_mask =
>    435				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
>    436				.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
>    437			}
>    438		}, {
>    439			.codec = HANTRO_HEVC_DECODER,
>    440			.cfg = {
>    441				.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
>    442				.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
>    443				.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
>    444				.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
>    445			},
>    446		}, {
>    447			.codec = HANTRO_HEVC_DECODER,
>    448			.cfg = {
>    449				.id = V4L2_CID_STATELESS_HEVC_START_CODE,
>    450				.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
>    451				.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
>    452				.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
>    453			},
>    454		}, {
>    455			.codec = HANTRO_HEVC_DECODER,
>    456			.cfg = {
>    457				.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
>    458				.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
>    459				.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
>    460				.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
>    461			},
>    462		}, {
>    463			.codec = HANTRO_HEVC_DECODER,
>    464			.cfg = {
>    465				.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
>    466				.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
>    467				.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
>    468			},
>    469		}, {
>    470			.codec = HANTRO_HEVC_DECODER,
>    471			.cfg = {
>    472				.id = V4L2_CID_STATELESS_HEVC_SPS,
>    473				.ops = &hantro_ctrl_ops,
>    474			},
>    475		}, {
>    476			.codec = HANTRO_HEVC_DECODER,
>    477			.cfg = {
>    478				.id = V4L2_CID_STATELESS_HEVC_PPS,
>    479			},
>    480		}, {
>    481			.codec = HANTRO_HEVC_DECODER,
>    482			.cfg = {
>    483				.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
>    484			},
>    485		}, {
>    486			.codec = HANTRO_HEVC_DECODER,
>    487			.cfg = {
>    488				.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
>    489			},
>    490		}, {
>    491			.codec = HANTRO_VP9_DECODER,
>    492			.cfg = {
>    493				.id = V4L2_CID_STATELESS_VP9_FRAME,
>    494				.ops = &hantro_vp9_ctrl_ops,
>    495			},
>    496		}, {
>    497			.codec = HANTRO_VP9_DECODER,
>    498			.cfg = {
>    499				.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
>    500			},
>    501		}, {
>    502			.codec = HANTRO_AV1_DECODER,
>    503			.cfg = {
>  > 504				.id = V4L2_CID_STATELESS_AV1_FRAME,
>    505			},
>    506		}, {
>    507			.codec = HANTRO_AV1_DECODER,
>    508			.cfg = {
>  > 509				.id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
>  > 510				.dims = { V4L2_AV1_MAX_TILE_COUNT },
>    511			},
>    512		}, {
>    513			.codec = HANTRO_AV1_DECODER,
>    514			.cfg = {
>  > 515				.id = V4L2_CID_STATELESS_AV1_SEQUENCE,
>    516			},
>    517		}, {
>    518			.codec = HANTRO_AV1_DECODER,
>    519			.cfg = {
>  > 520				.id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
>    521			},
>    522		},
>    523	};
>    524	
>
Nicolas Dufresne Dec. 19, 2022, 8:28 p.m. UTC | #3 
Le lundi 19 décembre 2022 à 16:56 +0100, Benjamin Gaignard a écrit :
> Add AV1 decoder as new decoder mode to Hantro driver.
> Register needed AV1 controls for the decoder.
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>

Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>

> ---
>  drivers/media/platform/verisilicon/hantro.h   |  3 +++
>  .../media/platform/verisilicon/hantro_drv.c   | 21 +++++++++++++++++++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h
> index 2989ebc631cc..61480825b856 100644
> --- a/drivers/media/platform/verisilicon/hantro.h
> +++ b/drivers/media/platform/verisilicon/hantro.h
> @@ -38,6 +38,7 @@ struct hantro_postproc_ops;
>  #define HANTRO_H264_DECODER	BIT(18)
>  #define HANTRO_HEVC_DECODER	BIT(19)
>  #define HANTRO_VP9_DECODER	BIT(20)
> +#define HANTRO_AV1_DECODER	BIT(21)
>  #define HANTRO_DECODERS		0xffff0000
>  
>  /**
> @@ -111,6 +112,7 @@ struct hantro_variant {
>   * @HANTRO_MODE_VP8_DEC: VP8 decoder.
>   * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
>   * @HANTRO_MODE_VP9_DEC: VP9 decoder.
> + * @HANTRO_MODE_AV1_DEC: AV1 decoder
>   */
>  enum hantro_codec_mode {
>  	HANTRO_MODE_NONE = -1,
> @@ -120,6 +122,7 @@ enum hantro_codec_mode {
>  	HANTRO_MODE_VP8_DEC,
>  	HANTRO_MODE_HEVC_DEC,
>  	HANTRO_MODE_VP9_DEC,
> +	HANTRO_MODE_AV1_DEC,
>  };
>  
>  /*
> diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
> index 8cb4a68c9119..4500e1fc0f2c 100644
> --- a/drivers/media/platform/verisilicon/hantro_drv.c
> +++ b/drivers/media/platform/verisilicon/hantro_drv.c
> @@ -498,6 +498,27 @@ static const struct hantro_ctrl controls[] = {
>  		.cfg = {
>  			.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
>  		},
> +	}, {
> +		.codec = HANTRO_AV1_DECODER,
> +		.cfg = {
> +			.id = V4L2_CID_STATELESS_AV1_FRAME,
> +		},
> +	}, {
> +		.codec = HANTRO_AV1_DECODER,
> +		.cfg = {
> +			.id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
> +			.dims = { V4L2_AV1_MAX_TILE_COUNT },
> +		},
> +	}, {
> +		.codec = HANTRO_AV1_DECODER,
> +		.cfg = {
> +			.id = V4L2_CID_STATELESS_AV1_SEQUENCE,
> +		},
> +	}, {
> +		.codec = HANTRO_AV1_DECODER,
> +		.cfg = {
> +			.id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
> +		},
>  	},
>  };
>
diff mbox series

Patch

diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h
index 2989ebc631cc..61480825b856 100644
--- a/drivers/media/platform/verisilicon/hantro.h
+++ b/drivers/media/platform/verisilicon/hantro.h
@@ -38,6 +38,7 @@  struct hantro_postproc_ops;
 #define HANTRO_H264_DECODER	BIT(18)
 #define HANTRO_HEVC_DECODER	BIT(19)
 #define HANTRO_VP9_DECODER	BIT(20)
+#define HANTRO_AV1_DECODER	BIT(21)
 #define HANTRO_DECODERS		0xffff0000
 
 /**
@@ -111,6 +112,7 @@  struct hantro_variant {
  * @HANTRO_MODE_VP8_DEC: VP8 decoder.
  * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
  * @HANTRO_MODE_VP9_DEC: VP9 decoder.
+ * @HANTRO_MODE_AV1_DEC: AV1 decoder
  */
 enum hantro_codec_mode {
 	HANTRO_MODE_NONE = -1,
@@ -120,6 +122,7 @@  enum hantro_codec_mode {
 	HANTRO_MODE_VP8_DEC,
 	HANTRO_MODE_HEVC_DEC,
 	HANTRO_MODE_VP9_DEC,
+	HANTRO_MODE_AV1_DEC,
 };
 
 /*
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
index 8cb4a68c9119..4500e1fc0f2c 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
+++ b/drivers/media/platform/verisilicon/hantro_drv.c
@@ -498,6 +498,27 @@  static const struct hantro_ctrl controls[] = {
 		.cfg = {
 			.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
 		},
+	}, {
+		.codec = HANTRO_AV1_DECODER,
+		.cfg = {
+			.id = V4L2_CID_STATELESS_AV1_FRAME,
+		},
+	}, {
+		.codec = HANTRO_AV1_DECODER,
+		.cfg = {
+			.id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
+			.dims = { V4L2_AV1_MAX_TILE_COUNT },
+		},
+	}, {
+		.codec = HANTRO_AV1_DECODER,
+		.cfg = {
+			.id = V4L2_CID_STATELESS_AV1_SEQUENCE,
+		},
+	}, {
+		.codec = HANTRO_AV1_DECODER,
+		.cfg = {
+			.id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
+		},
 	},
 };