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From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
To: matthias.bgg@gmail.com
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
tinghan.shen@mediatek.com, weiyi.lu@mediatek.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH 1/2] arm64: dts: mediatek: mt8195: Use P1 clocks for PCIe1
controller
Date: Wed, 14 Dec 2022 14:11:16 +0100
Message-Id: <20221214131117.108008-1-angelogioacchino.delregno@collabora.com>
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| Series |
[1/2] arm64: dts: mediatek: mt8195: Use P1 clocks for PCIe1 controller
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Commit Message
AngeloGioacchino Del Regno
Dec. 14, 2022, 1:11 p.m. UTC
Despite there being some flexibility regarding the P0/P1 connections,
especially for TL and PERI, we must use P1 clocks on pcie1 otherwise
we'll be dealing with unclocked access.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Comments
On 14/12/2022 14:11, AngeloGioacchino Del Regno wrote: > Despite there being some flexibility regarding the P0/P1 connections, > especially for TL and PERI, we must use P1 clocks on pcie1 otherwise > we'll be dealing with unclocked access. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Seems my mail got lost somewhere: Both patches applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 5d31536f4c48..e61944510b8e 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1258,9 +1258,9 @@ pcie1: pcie@112f8000 { > > clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, > <&clk26m>, > - <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, > + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, > <&clk26m>, > - <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, > + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, > /* Designer has connect pcie1 with peri_mem_p0 clock */ > <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; > clock-names = "pl_250m", "tl_26m", "tl_96m",
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c48..e61944510b8e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1258,9 +1258,9 @@ pcie1: pcie@112f8000 { clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, <&clk26m>, - <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, <&clk26m>, - <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, /* Designer has connect pcie1 with peri_mem_p0 clock */ <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; clock-names = "pl_250m", "tl_26m", "tl_96m",