| Message ID | 20221212123311.146261-12-manivannan.sadhasivam@linaro.org |
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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, bp@alien8.de,
tony.luck@intel.com
Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org,
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luca.weiss@fairphone.com,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
stable@vger.kernel.org
Subject: [PATCH v2 11/13] arm64: dts: qcom: sm6350: Remove reg-names property
from LLCC node
Date: Mon, 12 Dec 2022 18:03:09 +0530
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| Series |
Qcom: LLCC/EDAC: Fix base address used for LLCC banks
|
|
Commit Message
Manivannan Sadhasivam
Dec. 12, 2022, 12:33 p.m. UTC
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
On SM6350, there is only one LLCC bank available. So only change needed is
to remove the reg-names property from LLCC node to conform to the binding.
The driver is expected to parse the reg field based on index to get the
addresses of each LLCC banks.
Cc: <stable@vger.kernel.org> # 5.16
Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node")
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 -
1 file changed, 1 deletion(-)
Comments
On 12/12/2022 6:03 PM, Manivannan Sadhasivam wrote: > The LLCC block has several banks each with a different base address > and holes in between. So it is not a correct approach to cover these > banks with a single offset/size. Instead, the individual bank's base > address needs to be specified in devicetree with the exact size. > > On SM6350, there is only one LLCC bank available. So only change needed is > to remove the reg-names property from LLCC node to conform to the binding. > > The driver is expected to parse the reg field based on index to get the > addresses of each LLCC banks. > > Cc: <stable@vger.kernel.org> # 5.16 > Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node") > Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 43324bf291c3..1f39627cd7c6 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -1174,7 +1174,6 @@ dc_noc: interconnect@9160000 { > system-cache-controller@9200000 { > compatible = "qcom,sm6350-llcc"; > reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; > - reg-names = "llcc_base", "llcc_broadcast_base"; > }; > > gem_noc: interconnect@9680000 { Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
On 12/12/2022 13:33, Manivannan Sadhasivam wrote: > The LLCC block has several banks each with a different base address > and holes in between. So it is not a correct approach to cover these > banks with a single offset/size. Instead, the individual bank's base > address needs to be specified in devicetree with the exact size. > > On SM6350, there is only one LLCC bank available. So only change needed is > to remove the reg-names property from LLCC node to conform to the binding. > > The driver is expected to parse the reg field based on index to get the > addresses of each LLCC banks. > > Cc: <stable@vger.kernel.org> # 5.16 > Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node") This is a definitive no go. There is no bug here and such change cannot be backported. > Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> What is the bug here which deserves a credit? reg-names in v5.16 were perfectly correct. > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 43324bf291c3..1f39627cd7c6 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -1174,7 +1174,6 @@ dc_noc: interconnect@9160000 { > system-cache-controller@9200000 { > compatible = "qcom,sm6350-llcc"; > reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; > - reg-names = "llcc_base", "llcc_broadcast_base"; > }; > > gem_noc: interconnect@9680000 { Best regards, Krzysztof
On Tue, Dec 13, 2022 at 05:31:40PM +0100, Krzysztof Kozlowski wrote: > On 12/12/2022 13:33, Manivannan Sadhasivam wrote: > > The LLCC block has several banks each with a different base address > > and holes in between. So it is not a correct approach to cover these > > banks with a single offset/size. Instead, the individual bank's base > > address needs to be specified in devicetree with the exact size. > > > > On SM6350, there is only one LLCC bank available. So only change needed is > > to remove the reg-names property from LLCC node to conform to the binding. > > > > The driver is expected to parse the reg field based on index to get the > > addresses of each LLCC banks. > > > > Cc: <stable@vger.kernel.org> # 5.16 > > Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node") > > This is a definitive no go. There is no bug here and such change cannot > be backported. > > > Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> > > What is the bug here which deserves a credit? reg-names in v5.16 were > perfectly correct. > If the driver gets backported to v5.16, it won't. But anyway, this property will stay in dts. Thanks, Mani > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > > index 43324bf291c3..1f39627cd7c6 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > > @@ -1174,7 +1174,6 @@ dc_noc: interconnect@9160000 { > > system-cache-controller@9200000 { > > compatible = "qcom,sm6350-llcc"; > > reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; > > - reg-names = "llcc_base", "llcc_broadcast_base"; > > }; > > > > gem_noc: interconnect@9680000 { > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..1f39627cd7c6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,6 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 {