[10/15] dt-bindings: phy: qcom,qmp-pcie: add sc8280xp bindings

Message ID 20221017145328.22090-11-johan+linaro@kernel.org
State New
Headers
Series phy: qcom-qmp-pcie: add support for sc8280xp |

Commit Message

Johan Hovold Oct. 17, 2022, 2:53 p.m. UTC
  Add bindings for the PCIe QMP PHYs found on SC8280XP.

The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
PCIe2A and PCIe2B).

The configuration for a specific system can be read from a TCSR register.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 .../bindings/phy/qcom,qmp-pcie-phy.yaml       | 163 ++++++++++++++++++
 1 file changed, 163 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
  

Comments

Krzysztof Kozlowski Oct. 17, 2022, 5:20 p.m. UTC | #1
On 17/10/2022 10:53, Johan Hovold wrote:
> Add bindings for the PCIe QMP PHYs found on SC8280XP.
> 
> The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
> 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
> PCIe2A and PCIe2B).
> 
> The configuration for a specific system can be read from a TCSR register.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
>  .../bindings/phy/qcom,qmp-pcie-phy.yaml       | 163 ++++++++++++++++++
>  1 file changed, 163 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> new file mode 100644
> index 000000000000..82da95eaa9d6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml

Filename based on compatible, so for example:

qcom,sc8280xp-qmp-pcie-phy.yaml


> @@ -0,0 +1,163 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QMP PHY controller (PCIe)
> +
> +maintainers:
> +  - Vinod Koul <vkoul@kernel.org>
> +
> +description:
> +  QMP PHY controller supports physical layer functionality for a number of
> +  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> +      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> +      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clocks:
> +    maxItems: 6
> +
> +  clock-names:
> +    items:
> +      - const: aux
> +      - const: cfg_ahb
> +      - const: ref
> +      - const: rchng
> +      - const: pipe
> +      - const: pipediv2
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  reset-names:
> +    items:
> +      - const: phy
> +
> +  vdda-phy-supply: true
> +
> +  vdda-pll-supply: true
> +
> +  qcom,4ln-config-sel:
> +    description: 4-lane configuration as TCSR syscon phandle, register offset
> +                 and bit number
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      maxItems: 3

You have only one phandle, so you need to describe the items and limit
their number, like here:

https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42

This allows you to skip most of property description.

> +
> +  "#clock-cells":
> +    const: 0
> +
> +  clock-output-names:
> +    maxItems: 1
> +
> +  "#phy-cells":
> +    const: 0

Best regards,
Krzysztof
  
Johan Hovold Oct. 18, 2022, 9:40 a.m. UTC | #2
On Mon, Oct 17, 2022 at 01:20:49PM -0400, Krzysztof Kozlowski wrote:
> On 17/10/2022 10:53, Johan Hovold wrote:
> > Add bindings for the PCIe QMP PHYs found on SC8280XP.
> > 
> > The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
> > 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
> > PCIe2A and PCIe2B).
> > 
> > The configuration for a specific system can be read from a TCSR register.
> > 
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > ---
> >  .../bindings/phy/qcom,qmp-pcie-phy.yaml       | 163 ++++++++++++++++++
> >  1 file changed, 163 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..82da95eaa9d6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> 
> Filename based on compatible, so for example:
> 
> qcom,sc8280xp-qmp-pcie-phy.yaml

Ok, but as I mentioned in my reply to the previous patch, this file is
the one that is expected to be extended with new bindings.

I can't seem to find where this naming scheme is documented now even if
I'm quite sure I've seen it before. Do you have a pointer?

And does this imply that the file name should also include the gen infix
of one of the original compatibles (e.g.
"qcom,sc8280xp-qmp-gen3x4-pcie-phy.yaml")?

> > @@ -0,0 +1,163 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm QMP PHY controller (PCIe)
> > +
> > +maintainers:
> > +  - Vinod Koul <vkoul@kernel.org>
> > +
> > +description:
> > +  QMP PHY controller supports physical layer functionality for a number of
> > +  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> > +      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> > +      - qcom,sc8280xp-qmp-gen3x4-pcie-phy

> > +  qcom,4ln-config-sel:
> > +    description: 4-lane configuration as TCSR syscon phandle, register offset
> > +                 and bit number
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    items:
> > +      maxItems: 3
> 
> You have only one phandle, so you need to describe the items and limit
> their number, like here:
> 
> https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42
> 
> This allows you to skip most of property description.

Ah, thanks, makes perfect sense. I based this one of the in-tree
bindings which had been reviewed by Rob and must have thought it was
some special phandle-array notation to express the same.

Johan
  
Krzysztof Kozlowski Oct. 18, 2022, 3:22 p.m. UTC | #3
On 18/10/2022 05:40, Johan Hovold wrote:
> On Mon, Oct 17, 2022 at 01:20:49PM -0400, Krzysztof Kozlowski wrote:
>> On 17/10/2022 10:53, Johan Hovold wrote:
>>> Add bindings for the PCIe QMP PHYs found on SC8280XP.
>>>
>>> The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
>>> 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
>>> PCIe2A and PCIe2B).
>>>
>>> The configuration for a specific system can be read from a TCSR register.
>>>
>>> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
>>> ---
>>>  .../bindings/phy/qcom,qmp-pcie-phy.yaml       | 163 ++++++++++++++++++
>>>  1 file changed, 163 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
>>> new file mode 100644
>>> index 000000000000..82da95eaa9d6
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
>>
>> Filename based on compatible, so for example:
>>
>> qcom,sc8280xp-qmp-pcie-phy.yaml
> 
> Ok, but as I mentioned in my reply to the previous patch, this file is
> the one that is expected to be extended with new bindings.

I would still propose to use compatible of this series and treat it as a
family name of compatible or similar devices. What other choice we have?

If new (third) PHY bindings appear, then rename older to "-legacies" and
this one to "-legacy"?

> 
> I can't seem to find where this naming scheme is documented now even if
> I'm quite sure I've seen it before. Do you have a pointer?

If you need the source of authority, then:
https://lore.kernel.org/linux-devicetree/YlhkwvGdcf4ozTzG@robh.at.kernel.org/

If you need unofficial documentation, then slides here:
https://osseu2022.sched.com/event/15z0W

If you need something official, that's on TODO list. :)

> 
> And does this imply that the file name should also include the gen infix
> of one of the original compatibles (e.g.
> "qcom,sc8280xp-qmp-gen3x4-pcie-phy.yaml")?

Since you already have here three compatibles, you cannot have one
filename matching exactly all of them, so we already accept something
generic. Therefore I proposed the common part - matching SoC component.

Best regards,
Krzysztof
  
Johan Hovold Oct. 18, 2022, 3:47 p.m. UTC | #4
On Tue, Oct 18, 2022 at 11:22:13AM -0400, Krzysztof Kozlowski wrote:
> On 18/10/2022 05:40, Johan Hovold wrote:
> > On Mon, Oct 17, 2022 at 01:20:49PM -0400, Krzysztof Kozlowski wrote:
> >> On 17/10/2022 10:53, Johan Hovold wrote:
> >>> Add bindings for the PCIe QMP PHYs found on SC8280XP.

> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
> >>
> >> Filename based on compatible, so for example:
> >>
> >> qcom,sc8280xp-qmp-pcie-phy.yaml
> > 
> > Ok, but as I mentioned in my reply to the previous patch, this file is
> > the one that is expected to be extended with new bindings.
> 
> I would still propose to use compatible of this series and treat it as a
> family name of compatible or similar devices. What other choice we have?
> 
> If new (third) PHY bindings appear, then rename older to "-legacies" and
> this one to "-legacy"?

We could also continue using

	qcom,qmp-pcie-phy.yaml

for the latest generic binding were new devices should be added and
rename the "deprecated" ones after one of the compatibles to make it
sound less generic.

But I get your point.
	
> > I can't seem to find where this naming scheme is documented now even if
> > I'm quite sure I've seen it before. Do you have a pointer?
> 
> If you need the source of authority, then:
> https://lore.kernel.org/linux-devicetree/YlhkwvGdcf4ozTzG@robh.at.kernel.org/
> 
> If you need unofficial documentation, then slides here:
> https://osseu2022.sched.com/event/15z0W
> 
> If you need something official, that's on TODO list. :)

Heh. Ok.

> > And does this imply that the file name should also include the gen infix
> > of one of the original compatibles (e.g.
> > "qcom,sc8280xp-qmp-gen3x4-pcie-phy.yaml")?
> 
> Since you already have here three compatibles, you cannot have one
> filename matching exactly all of them, so we already accept something
> generic. Therefore I proposed the common part - matching SoC component.

Yeah, that's what I was alluding too. As soon you add one more SoC to
the same document, the common part is no longer

	qcom,sc8280xp-qmp-pcie-phy

but rather

	qcom,qmp-pcie-phy

Johan
  

Patch

diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
new file mode 100644
index 000000000000..82da95eaa9d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
@@ -0,0 +1,163 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP PHY controller (PCIe)
+
+maintainers:
+  - Vinod Koul <vkoul@kernel.org>
+
+description:
+  QMP PHY controller supports physical layer functionality for a number of
+  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
+      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
+      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  clocks:
+    maxItems: 6
+
+  clock-names:
+    items:
+      - const: aux
+      - const: cfg_ahb
+      - const: ref
+      - const: rchng
+      - const: pipe
+      - const: pipediv2
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    items:
+      - const: phy
+
+  vdda-phy-supply: true
+
+  vdda-pll-supply: true
+
+  qcom,4ln-config-sel:
+    description: 4-lane configuration as TCSR syscon phandle, register offset
+                 and bit number
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      maxItems: 3
+
+  "#clock-cells":
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+  - reset-names
+  - vdda-phy-supply
+  - vdda-pll-supply
+  - "#clock-cells"
+  - clock-output-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
+    then:
+      properties:
+        reg:
+          items:
+            - description: port a
+            - description: port b
+      required:
+        - qcom,4ln-config-sel
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+
+    pcie2b_phy: phy@1c18000 {
+      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
+      reg = <0x01c18000 0x2000>;
+
+      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
+               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
+               <&gcc GCC_PCIE_2B_PIPE_CLK>,
+               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
+      clock-names = "aux", "cfg_ahb", "ref", "rchng",
+                    "pipe", "pipediv2";
+
+      power-domains = <&gcc PCIE_2B_GDSC>;
+
+      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
+      reset-names = "phy";
+
+      vdda-phy-supply = <&vreg_l6d>;
+      vdda-pll-supply = <&vreg_l4d>;
+
+      #clock-cells = <0>;
+      clock-output-names = "pcie_2b_pipe_clk";
+
+      #phy-cells = <0>;
+    };
+
+    pcie2a_phy: phy@1c24000 {
+      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
+      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
+
+      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
+               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
+               <&gcc GCC_PCIE_2A_PIPE_CLK>,
+               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
+      clock-names = "aux", "cfg_ahb", "ref", "rchng",
+                    "pipe", "pipediv2";
+
+      power-domains = <&gcc PCIE_2A_GDSC>;
+
+      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
+      reset-names = "phy";
+
+      vdda-phy-supply = <&vreg_l6d>;
+      vdda-pll-supply = <&vreg_l4d>;
+
+      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
+
+      #clock-cells = <0>;
+      clock-output-names = "pcie_2a_pipe_clk";
+
+      #phy-cells = <0>;
+    };