[v6,tty-next,3/4] serial: 8250_pci1xxxx: Add RS485 support to quad-uart driver
Commit Message
pci1xxxx uart supports RS485 mode of operation in the hardware with
auto-direction control with configurable delay for releasing RTS after
the transmission. This patch adds support for the RS485 mode.
Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
---
Changes in v6:
- Modified datatype of delay_in_baud_periods to u64 to avoid overflows
Changes in v5:
- Removed unnecessary assignments
- Corrected styling issues in comments
Changes in v4:
- No Change
Changes in v3:
- Remove flags sanitization in driver which is taken care in core
Changes in v2:
- move pci1xxxx_rs485_config to a separate patch with
pci1xxxx_rs485_supported.
---
drivers/tty/serial/8250/8250_pci1xxxx.c | 49 +++++++++++++++++++++++++
1 file changed, 49 insertions(+)
Comments
On Thu, 1 Dec 2022, Kumaravel Thiagarajan wrote:
> pci1xxxx uart supports RS485 mode of operation in the hardware with
> auto-direction control with configurable delay for releasing RTS after
> the transmission. This patch adds support for the RS485 mode.
>
> Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
> Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
> Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
> ---
> Changes in v6:
> - Modified datatype of delay_in_baud_periods to u64 to avoid overflows
>
> Changes in v5:
> - Removed unnecessary assignments
> - Corrected styling issues in comments
>
> Changes in v4:
> - No Change
>
> Changes in v3:
> - Remove flags sanitization in driver which is taken care in core
>
> Changes in v2:
> - move pci1xxxx_rs485_config to a separate patch with
> pci1xxxx_rs485_supported.
> ---
> drivers/tty/serial/8250/8250_pci1xxxx.c | 49 +++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c
> index d5037e76b636..7585066d6baf 100644
> --- a/drivers/tty/serial/8250/8250_pci1xxxx.c
> +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
> @@ -145,6 +145,53 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud,
> port->membase + UART_BAUD_CLK_DIVISOR_REG);
> }
>
> +static int pci1xxxx_rs485_config(struct uart_port *port,
> + struct ktermios *termios,
> + struct serial_rs485 *rs485)
> +{
> + u32 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);
Maybe move this into the block where it's needed?
> + u64 delay_in_baud_periods;
> + u32 baud_period_in_ns;
> + u32 data = 0;
data seems a bit too generic name for a variable? At minimum I'd suggest
using cfg or mode_cfg (I couldn't guess where ADCL comes from, perhaps it
has some component which would make the variable name better).
> +
> + /*
> + * pci1xxxx's uart hardware supports only RTS delay after
> + * Tx and in units of bit times to a maximum of 15
> + */
> + if (rs485->flags & SER_RS485_ENABLED) {
> + data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;
> +
> + if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
> + data |= ADCL_CFG_POL_SEL;
> +
> + if (rs485->delay_rts_after_send) {
> + baud_period_in_ns =
> + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) *
> + UART_BIT_SAMPLE_CNT;
> + delay_in_baud_periods =
> + rs485->delay_rts_after_send * NSEC_PER_MSEC /
> + baud_period_in_ns;
> + delay_in_baud_periods =
> + min_t(u64, delay_in_baud_periods,
> + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));
> + data |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK,
> + delay_in_baud_periods);
> + rs485->delay_rts_after_send =
> + baud_period_in_ns * delay_in_baud_periods /
> + NSEC_PER_MSEC;
> + }
> + }
> + writel(data, port->membase + ADCL_CFG_REG);
> + return 0;
> +}
> +
> +static const struct serial_rs485 pci1xxxx_rs485_supported = {
> + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
> + SER_RS485_RTS_AFTER_SEND,
> + .delay_rts_after_send = 1,
> + /* Delay RTS before send is not supported */
> +};
> +
> static int pci1xxxx_setup(struct pci1xxxx_8250 *priv,
> struct uart_8250_port *port, int port_idx)
> {
> @@ -155,6 +202,8 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv,
> port->port.set_termios = serial8250_do_set_termios;
> port->port.get_divisor = pci1xxxx_get_divisor;
> port->port.set_divisor = pci1xxxx_set_divisor;
> + port->port.rs485_config = pci1xxxx_rs485_config;
> + port->port.rs485_supported = pci1xxxx_rs485_supported;
>
> ret = serial8250_pci_setup_port(priv->pdev, port, 0, port_idx * 256, 0);
> if (ret < 0)
>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> -----Original Message-----
> From: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> Sent: Thursday, December 1, 2022 3:17 PM
> To: Kumaravel Thiagarajan - I21417 <Kumaravel.Thiagarajan@microchip.com>
> Subject: Re: [PATCH v6 tty-next 3/4] serial: 8250_pci1xxxx: Add RS485
> support to quad-uart driver
>
> On Thu, 1 Dec 2022, Kumaravel Thiagarajan wrote:
>
> > pci1xxxx uart supports RS485 mode of operation in the hardware with
> > auto-direction control with configurable delay for releasing RTS after
> > the transmission. This patch adds support for the RS485 mode.
> >
> >
> > +static int pci1xxxx_rs485_config(struct uart_port *port,
> > + struct ktermios *termios,
> > + struct serial_rs485 *rs485) {
> > + u32 clock_div = readl(port->membase +
> > +UART_BAUD_CLK_DIVISOR_REG);
>
> Maybe move this into the block where it's needed?
>
> > + u64 delay_in_baud_periods;
> > + u32 baud_period_in_ns;
> > + u32 data = 0;
>
> data seems a bit too generic name for a variable? At minimum I'd suggest
> using cfg or mode_cfg (I couldn't guess where ADCL comes from, perhaps it
> has some component which would make the variable name better).
Hi Ilpo,
We just noticed after submitting v7 that this email of yours got forwarded to spam folder by our IT infrastructure automatically and we missed it.
We will take care of this in v8.
Thank You.
Regards,
Kumar
@@ -145,6 +145,53 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud,
port->membase + UART_BAUD_CLK_DIVISOR_REG);
}
+static int pci1xxxx_rs485_config(struct uart_port *port,
+ struct ktermios *termios,
+ struct serial_rs485 *rs485)
+{
+ u32 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);
+ u64 delay_in_baud_periods;
+ u32 baud_period_in_ns;
+ u32 data = 0;
+
+ /*
+ * pci1xxxx's uart hardware supports only RTS delay after
+ * Tx and in units of bit times to a maximum of 15
+ */
+ if (rs485->flags & SER_RS485_ENABLED) {
+ data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;
+
+ if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
+ data |= ADCL_CFG_POL_SEL;
+
+ if (rs485->delay_rts_after_send) {
+ baud_period_in_ns =
+ FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) *
+ UART_BIT_SAMPLE_CNT;
+ delay_in_baud_periods =
+ rs485->delay_rts_after_send * NSEC_PER_MSEC /
+ baud_period_in_ns;
+ delay_in_baud_periods =
+ min_t(u64, delay_in_baud_periods,
+ FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));
+ data |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK,
+ delay_in_baud_periods);
+ rs485->delay_rts_after_send =
+ baud_period_in_ns * delay_in_baud_periods /
+ NSEC_PER_MSEC;
+ }
+ }
+ writel(data, port->membase + ADCL_CFG_REG);
+ return 0;
+}
+
+static const struct serial_rs485 pci1xxxx_rs485_supported = {
+ .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
+ SER_RS485_RTS_AFTER_SEND,
+ .delay_rts_after_send = 1,
+ /* Delay RTS before send is not supported */
+};
+
static int pci1xxxx_setup(struct pci1xxxx_8250 *priv,
struct uart_8250_port *port, int port_idx)
{
@@ -155,6 +202,8 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv,
port->port.set_termios = serial8250_do_set_termios;
port->port.get_divisor = pci1xxxx_get_divisor;
port->port.set_divisor = pci1xxxx_set_divisor;
+ port->port.rs485_config = pci1xxxx_rs485_config;
+ port->port.rs485_supported = pci1xxxx_rs485_supported;
ret = serial8250_pci_setup_port(priv->pdev, port, 0, port_idx * 256, 0);
if (ret < 0)