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[1/2] x86/pat: fix TDX guest PAT initialization

Message ID 20221205080433.16643-2-jgross@suse.com
State New
Headers
Series x86: fixes for MTRR/PAT decoupling |

Commit Message

Juergen Gross Dec. 5, 2022, 8:04 a.m. UTC 
  With the decoupling of PAT and MTRR initialization, PAT will be used
even with MTRRs disabled. This seems to break booting up as TDX guest,
as the recommended sequence to set the PAT MSR across CPUs can't work
in TDX guests due to disabling caches via setting CR0.CD isn't allowed
in TDX mode.

This is an inconsistency in the Intel documentation between the SDM
and the TDX specification. For now handle TDX mode the same way as Xen
PV guest mode by just accepting the current PAT MSR setting without
trying to modify it.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/mm/pat/memtype.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Kirill A. Shutemov Dec. 5, 2022, 12:26 p.m. UTC | #1 
On Mon, Dec 05, 2022 at 09:04:32AM +0100, Juergen Gross wrote:
> With the decoupling of PAT and MTRR initialization, PAT will be used
> even with MTRRs disabled. This seems to break booting up as TDX guest,
> as the recommended sequence to set the PAT MSR across CPUs can't work
> in TDX guests due to disabling caches via setting CR0.CD isn't allowed
> in TDX mode.
> 
> This is an inconsistency in the Intel documentation between the SDM
> and the TDX specification. For now handle TDX mode the same way as Xen
> PV guest mode by just accepting the current PAT MSR setting without
> trying to modify it.
> 
> Signed-off-by: Juergen Gross <jgross@suse.com>

Good enough for now. I will follow up if something comes up from the
discussion around the topic.

Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

> ---
>  arch/x86/mm/pat/memtype.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
> index 9aab17d660cd..4e50add760ad 100644
> --- a/arch/x86/mm/pat/memtype.c
> +++ b/arch/x86/mm/pat/memtype.c
> @@ -296,8 +296,12 @@ void __init pat_bp_init(void)
>  	/*
>  	 * Xen PV doesn't allow to set PAT MSR, but all cache modes are
>  	 * supported.
> +	 * When running as TDX guest setting the PAT MSR won't work either
> +	 * due to the requirement to set CR0.CD when doing so. Rely on
> +	 * firmware to have set the PAT MSR correctly.

s/firmware/TDX module/

>  	 */
> -	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
> +	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV) ||
> +	    cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
>  		init_cache_modes(pat_msr_val);
>  		return;
>  	}
diff mbox series

Patch

diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index 9aab17d660cd..4e50add760ad 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -296,8 +296,12 @@  void __init pat_bp_init(void)
 	/*
 	 * Xen PV doesn't allow to set PAT MSR, but all cache modes are
 	 * supported.
+	 * When running as TDX guest setting the PAT MSR won't work either
+	 * due to the requirement to set CR0.CD when doing so. Rely on
+	 * firmware to have set the PAT MSR correctly.
 	 */
-	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
+	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV) ||
+	    cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
 		init_cache_modes(pat_msr_val);
 		return;
 	}