Message ID | 20221118011714.70877-9-hal.feng@starfivetech.com |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b7-20020a056402084700b004690009024csi1261050edz.503.2022.11.17.17.37.09; Thu, 17 Nov 2022 17:37:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240934AbiKRBfg convert rfc822-to-8bit (ORCPT <rfc822;a1648639935@gmail.com> + 99 others); Thu, 17 Nov 2022 20:35:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240813AbiKRBfZ (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 17 Nov 2022 20:35:25 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49BB46379; Thu, 17 Nov 2022 17:35:12 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id BBCF424E0F4; Fri, 18 Nov 2022 09:17:24 +0800 (CST) Received: from EXMBX072.cuchost.com (172.16.6.82) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 18 Nov 2022 09:17:24 +0800 Received: from ubuntu.localdomain (183.27.96.116) by EXMBX072.cuchost.com (172.16.6.82) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 18 Nov 2022 09:17:23 +0800 From: Hal Feng <hal.feng@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org> CC: Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Linus Walleij" <linus.walleij@linaro.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW Date: Fri, 18 Nov 2022 09:17:14 +0800 Message-ID: <20221118011714.70877-9-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221118011714.70877-1-hal.feng@starfivetech.com> References: <20221118011714.70877-1-hal.feng@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [183.27.96.116] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX072.cuchost.com (172.16.6.82) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749795947014406859?= X-GMAIL-MSGID: =?utf-8?q?1749795947014406859?= |
Series |
Basic device tree support for StarFive JH7110 RISC-V SoC
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Commit Message
Hal Feng
Nov. 18, 2022, 1:17 a.m. UTC
Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
Comments
Hey Palmer, Can you take this patch for v6.2 please, as it kinda just equalises things for the existing jh7100 stuff? Everyone else can boot defconfig other than the visionfive v1/beagle v. Thanks, Conor. On Fri, Nov 18, 2022 at 09:17:14AM +0800, Hal Feng wrote: > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for > StarFive JH7110 and JH7100 SoCs to boot with serial ports. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > arch/riscv/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index 05fd5fcf24f9..a23d022974ad 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y > CONFIG_INPUT_MOUSEDEV=y > CONFIG_SERIAL_8250=y > CONFIG_SERIAL_8250_CONSOLE=y > +CONFIG_SERIAL_8250_DW=y > CONFIG_SERIAL_OF_PLATFORM=y > CONFIG_VIRTIO_CONSOLE=y > CONFIG_HW_RANDOM=y > -- > 2.38.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Thu, 17 Nov 2022 17:17:14 PST (-0800), hal.feng@starfivetech.com wrote: > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for > StarFive JH7110 and JH7100 SoCs to boot with serial ports. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > arch/riscv/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index 05fd5fcf24f9..a23d022974ad 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y > CONFIG_INPUT_MOUSEDEV=y > CONFIG_SERIAL_8250=y > CONFIG_SERIAL_8250_CONSOLE=y > +CONFIG_SERIAL_8250_DW=y > CONFIG_SERIAL_OF_PLATFORM=y > CONFIG_VIRTIO_CONSOLE=y > CONFIG_HW_RANDOM=y Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote: > On Thu, 17 Nov 2022 17:17:14 PST (-0800), hal.feng@starfivetech.com wrote: > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for > > StarFive JH7110 and JH7100 SoCs to boot with serial ports. > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > arch/riscv/configs/defconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > > index 05fd5fcf24f9..a23d022974ad 100644 > > --- a/arch/riscv/configs/defconfig > > +++ b/arch/riscv/configs/defconfig > > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y > > CONFIG_INPUT_MOUSEDEV=y > > CONFIG_SERIAL_8250=y > > CONFIG_SERIAL_8250_CONSOLE=y > > +CONFIG_SERIAL_8250_DW=y > > CONFIG_SERIAL_OF_PLATFORM=y > > CONFIG_VIRTIO_CONSOLE=y > > CONFIG_HW_RANDOM=y > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Hey Palmer, could you take this as v6.2 material instead of Acking it please? It applies to the jh7100 stuff that's already in-tree. Thanks!
On Fri, 02 Dec 2022 10:07:33 PST (-0800), Conor Dooley wrote: > On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote: >> On Thu, 17 Nov 2022 17:17:14 PST (-0800), hal.feng@starfivetech.com wrote: >> > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for >> > StarFive JH7110 and JH7100 SoCs to boot with serial ports. >> > >> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> > --- >> > arch/riscv/configs/defconfig | 1 + >> > 1 file changed, 1 insertion(+) >> > >> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig >> > index 05fd5fcf24f9..a23d022974ad 100644 >> > --- a/arch/riscv/configs/defconfig >> > +++ b/arch/riscv/configs/defconfig >> > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y >> > CONFIG_INPUT_MOUSEDEV=y >> > CONFIG_SERIAL_8250=y >> > CONFIG_SERIAL_8250_CONSOLE=y >> > +CONFIG_SERIAL_8250_DW=y >> > CONFIG_SERIAL_OF_PLATFORM=y >> > CONFIG_VIRTIO_CONSOLE=y >> > CONFIG_HW_RANDOM=y >> >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > Hey Palmer, could you take this as v6.2 material instead of Acking it > please? It applies to the jh7100 stuff that's already in-tree. Ya, no problem. Just this patch, or the whole series?
On Fri, Dec 02, 2022 at 10:13:40AM -0800, Palmer Dabbelt wrote: > On Fri, 02 Dec 2022 10:07:33 PST (-0800), Conor Dooley wrote: > > On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote: > > > On Thu, 17 Nov 2022 17:17:14 PST (-0800), hal.feng@starfivetech.com wrote: > > > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for > > > > StarFive JH7110 and JH7100 SoCs to boot with serial ports. > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > > > --- > > > > arch/riscv/configs/defconfig | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > diff --git a/arch/riscv/configs/defconfig > > > b/arch/riscv/configs/defconfig > > > > index 05fd5fcf24f9..a23d022974ad 100644 > > > > --- a/arch/riscv/configs/defconfig > > > > +++ b/arch/riscv/configs/defconfig > > > > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y > > > > CONFIG_INPUT_MOUSEDEV=y > > > > CONFIG_SERIAL_8250=y > > > > CONFIG_SERIAL_8250_CONSOLE=y > > > > +CONFIG_SERIAL_8250_DW=y > > > > CONFIG_SERIAL_OF_PLATFORM=y > > > > CONFIG_VIRTIO_CONSOLE=y > > > > CONFIG_HW_RANDOM=y > > > > > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > > > Hey Palmer, could you take this as v6.2 material instead of Acking it > > please? It applies to the jh7100 stuff that's already in-tree. > > Ya, no problem. Just this patch, or the whole series? Just this one defconfig patch please, the rest is not ready. Sorry that that was not clear, Conor.
On Fri, 02 Dec 2022 10:18:21 PST (-0800), Conor Dooley wrote: > On Fri, Dec 02, 2022 at 10:13:40AM -0800, Palmer Dabbelt wrote: >> On Fri, 02 Dec 2022 10:07:33 PST (-0800), Conor Dooley wrote: >> > On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote: >> > > On Thu, 17 Nov 2022 17:17:14 PST (-0800), hal.feng@starfivetech.com wrote: >> > > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for >> > > > StarFive JH7110 and JH7100 SoCs to boot with serial ports. >> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >> > > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> > > > --- >> > > > arch/riscv/configs/defconfig | 1 + >> > > > 1 file changed, 1 insertion(+) >> > > > > diff --git a/arch/riscv/configs/defconfig >> > > b/arch/riscv/configs/defconfig >> > > > index 05fd5fcf24f9..a23d022974ad 100644 >> > > > --- a/arch/riscv/configs/defconfig >> > > > +++ b/arch/riscv/configs/defconfig >> > > > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y >> > > > CONFIG_INPUT_MOUSEDEV=y >> > > > CONFIG_SERIAL_8250=y >> > > > CONFIG_SERIAL_8250_CONSOLE=y >> > > > +CONFIG_SERIAL_8250_DW=y >> > > > CONFIG_SERIAL_OF_PLATFORM=y >> > > > CONFIG_VIRTIO_CONSOLE=y >> > > > CONFIG_HW_RANDOM=y >> > > >> > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> >> > >> > Hey Palmer, could you take this as v6.2 material instead of Acking it >> > please? It applies to the jh7100 stuff that's already in-tree. >> >> Ya, no problem. Just this patch, or the whole series? > > Just this one defconfig patch please, the rest is not ready. > Sorry that that was not clear, No problem. It's staged, it'll end up on for-next when it builds (it's behind some other stuff right now).
On Fri, 18 Nov 2022 09:17:14 +0800, Hal Feng wrote: > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for > StarFive JH7110 and JH7100 SoCs to boot with serial ports. > > Applied, thanks! [8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW https://git.kernel.org/palmer/c/6925ba3d9b8c Best regards,
On Fri, 02 Dec 2022 10:43:06 -0800, Palmer Dabbelt wrote: > On Fri, 18 Nov 2022 09:17:14 +0800, Hal Feng wrote: > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for > > StarFive JH7110 and JH7100 SoCs to boot with serial ports. > > > > > > Applied, thanks! Thank you so much! Best regards, Hal > > [8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW > https://git.kernel.org/palmer/c/6925ba3d9b8c
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..a23d022974ad 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y