diff mbox series

[v8,10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors

Message ID 20221201225703.6507-11-ddrokosov@sberdevices.ru
State New
Headers
Series add Amlogic A1 clock controller drivers |

Commit Message

Dmitry Rokosov Dec. 1, 2022, 10:57 p.m. UTC 
  During running dtbs_check and dt_binding_check checkers the following
problems were found and resolved:
    - $id is not correct, it has wrong url path
    - no base offset in the dt node definition
    - CLKIDs aren't applied by names, just magic int constants there
    - address and size cells are required for long reg definition
    - wrong indentations

Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
 .../bindings/clock/amlogic,a1-clkc.yaml       | 36 +++++++++++--------
 1 file changed, 22 insertions(+), 14 deletions(-)

Comments

Krzysztof Kozlowski Dec. 2, 2022, 10:40 a.m. UTC | #1 
On 01/12/2022 23:57, Dmitry Rokosov wrote:
> During running dtbs_check and dt_binding_check checkers the following
> problems were found and resolved:
>     - $id is not correct, it has wrong url path
>     - no base offset in the dt node definition
>     - CLKIDs aren't applied by names, just magic int constants there
>     - address and size cells are required for long reg definition
>     - wrong indentations
> 
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
>  .../bindings/clock/amlogic,a1-clkc.yaml       | 36 +++++++++++--------
>  1 file changed, 22 insertions(+), 14 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> index 7729850046cf..b0249ab21466 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> @@ -1,7 +1,7 @@
> -#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>  %YAML 1.2
>  ---
> -$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#"
> +$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#"
>  $schema: "http://devicetree.org/meta-schemas/core.yaml#"
>  

NAK. This must be squashed.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
index 7729850046cf..b0249ab21466 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -1,7 +1,7 @@ 
-#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#"
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
 title: Amlogic Meson A/C serials Peripheral Clock Control Unit Device Tree Bindings
@@ -10,6 +10,7 @@  maintainers:
   - Neil Armstrong <narmstrong@baylibre.com>
   - Jerome Brunet <jbrunet@baylibre.com>
   - Jian Hu <jian.hu@jian.hu.com>
+  - Dmitry Rokosov <ddrokosov@sberdevices.ru>
 
 properties:
   compatible:
@@ -50,16 +51,23 @@  additionalProperties: false
 
 examples:
   - |
-    clkc_periphs: periphs-clock-controller {
-        compatible = "amlogic,a1-periphs-clkc";
-        reg = <0 0x800 0 0x104>;
-        #clock-cells = <1>;
-        clocks = <&clkc_pll 6>,
-                <&clkc_pll 7>,
-                <&clkc_pll 8>,
-                <&clkc_pll 9>,
-                <&clkc_pll 10>,
-                <&xtal>;
-        clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
-                      "fclk_div7", "hifi_pll", "xtal";
+    #include <dt-bindings/clock/a1-pll-clkc.h>
+    apb {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clkc_periphs: periphs-clock-controller@800 {
+            compatible = "amlogic,a1-periphs-clkc";
+            reg = <0 0x800 0 0x104>;
+            #clock-cells = <1>;
+            clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+                     <&clkc_pll CLKID_FCLK_DIV3>,
+                     <&clkc_pll CLKID_FCLK_DIV5>,
+                     <&clkc_pll CLKID_FCLK_DIV7>,
+                     <&clkc_pll CLKID_HIFI_PLL>,
+                     <&xtal>;
+            clock-names = "fclk_div2", "fclk_div3",
+                          "fclk_div5", "fclk_div7",
+                          "hifi_pll", "xtal";
+        };
     };