diff mbox series

RISC-V: Move certain arrays to riscv-opc.c

Message ID d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com
State Accepted, archived
Headers
Series RISC-V: Move certain arrays to riscv-opc.c |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Tsukasa OI Oct. 9, 2022, 5:09 a.m. UTC 
  This is a part of small tidying (declare tables in riscv-opc.c).

include/ChangeLog:

	* opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to
	opcodes/riscv-opc.c.  New non-static definitions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_rm, riscv_pred_succ): Move from
	include/opcode/riscv.h.  Add description.
---
 include/opcode/riscv.h | 13 ++-----------
 opcodes/riscv-opc.c    | 13 +++++++++++++
 2 files changed, 15 insertions(+), 11 deletions(-)


base-commit: c10a862f17847bc9c50d680c87b87dc51ae4b95e

Comments

Nelson Chu Oct. 14, 2022, 3:09 a.m. UTC | #1 
OK, test cases passed, please commit.

Thanks
Nelson

On Sun, Oct 9, 2022 at 1:09 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This is a part of small tidying (declare tables in riscv-opc.c).
>
> include/ChangeLog:
>
>         * opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to
>         opcodes/riscv-opc.c.  New non-static definitions.
>
> opcodes/ChangeLog:
>
>         * riscv-opc.c (riscv_rm, riscv_pred_succ): Move from
>         include/opcode/riscv.h.  Add description.
> ---
>  include/opcode/riscv.h | 13 ++-----------
>  opcodes/riscv-opc.c    | 13 +++++++++++++
>  2 files changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index f173a2eca25..dddabfdd415 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -46,17 +46,6 @@ static inline unsigned int riscv_insn_length (insn_t insn)
>    return 2;
>  }
>
> -static const char * const riscv_rm[8] =
> -{
> -  "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
> -};
> -
> -static const char * const riscv_pred_succ[16] =
> -{
> -  0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
> -  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
> -};
> -
>  #define RVC_JUMP_BITS 11
>  #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
>
> @@ -555,6 +544,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR];
>  extern const char * const riscv_gpr_names_abi[NGPR];
>  extern const char * const riscv_fpr_names_numeric[NFPR];
>  extern const char * const riscv_fpr_names_abi[NFPR];
> +extern const char * const riscv_rm[8];
> +extern const char * const riscv_pred_succ[16];
>  extern const char * const riscv_vecr_names_numeric[NVECR];
>  extern const char * const riscv_vecm_names_numeric[NVECM];
>  extern const char * const riscv_vsew[8];
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 11bb87d7eaa..04acc8470be 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -58,6 +58,19 @@ const char * const riscv_fpr_names_abi[NFPR] =
>    "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11"
>  };
>
> +/* Rounding modes.  */
> +const char * const riscv_rm[8] =
> +{
> +  "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
> +};
> +
> +/* FENCE: predecessor/successor sets.  */
> +const char * const riscv_pred_succ[16] =
> +{
> +  0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
> +  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
> +};
> +
>  /* RVV registers.  */
>  const char * const riscv_vecr_names_numeric[NVECR] =
>  {
>
> base-commit: c10a862f17847bc9c50d680c87b87dc51ae4b95e
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index f173a2eca25..dddabfdd415 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -46,17 +46,6 @@  static inline unsigned int riscv_insn_length (insn_t insn)
   return 2;
 }
 
-static const char * const riscv_rm[8] =
-{
-  "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
-};
-
-static const char * const riscv_pred_succ[16] =
-{
-  0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
-  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
-};
-
 #define RVC_JUMP_BITS 11
 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
 
@@ -555,6 +544,8 @@  extern const char * const riscv_gpr_names_numeric[NGPR];
 extern const char * const riscv_gpr_names_abi[NGPR];
 extern const char * const riscv_fpr_names_numeric[NFPR];
 extern const char * const riscv_fpr_names_abi[NFPR];
+extern const char * const riscv_rm[8];
+extern const char * const riscv_pred_succ[16];
 extern const char * const riscv_vecr_names_numeric[NVECR];
 extern const char * const riscv_vecm_names_numeric[NVECM];
 extern const char * const riscv_vsew[8];
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 11bb87d7eaa..04acc8470be 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -58,6 +58,19 @@  const char * const riscv_fpr_names_abi[NFPR] =
   "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11"
 };
 
+/* Rounding modes.  */
+const char * const riscv_rm[8] =
+{
+  "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
+};
+
+/* FENCE: predecessor/successor sets.  */
+const char * const riscv_pred_succ[16] =
+{
+  0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
+  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
+};
+
 /* RVV registers.  */
 const char * const riscv_vecr_names_numeric[NVECR] =
 {