diff mbox series

[10/20] arm64: dts: Update cache properties for marvell

Message ID	20221031092020.532456-1-pierre.gondois@arm.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Pierre Gondois <pierre.gondois@arm.com> To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Andrew Lunn <andrew@lunn.ch>, Gregory Clement <gregory.clement@bootlin.com>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Vadym Kochan <vadym.kochan@plvision.eu>, Chris Packham <chris.packham@alliedtelesis.co.nz>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/20] arm64: dts: Update cache properties for marvell Date: Mon, 31 Oct 2022 10:20:16 +0100 Message-Id: <20221031092020.532456-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Update cache properties for arm64 DTS \| [00/20] Update cache properties for arm64 DTS [01/20] arm64: dts: Update cache properties for amd [02/20] arm64: dts: Update cache properties for amlogic [03/20] arm64: dts: Update cache properties for apm [04/20] arm64: dts: Update cache properties for arm [05/20] arm64: dts: Update cache properties for broadcom [06/20] arm64: dts: Update cache properties for exynos [07/20] arm64: dts: Update cache properties for freescale [08/20] arm64: dts: Update cache properties for hisilicon [09/20] arm64: dts: Update cache properties for lg [10/20] arm64: dts: Update cache properties for marvell [11/20] arm64: dts: Update cache properties for mediatek [12/20] arm64: dts: Update cache properties for microchip [13/20] arm64: dts: Update cache properties for nuvoton [14/20] arm64: dts: Update cache properties for nvidia [15/20] arm64: dts: Update cache properties for qcom [16/20] arm64: dts: Update cache properties for realtek [17/20] arm64: dts: Update cache properties for renesas [18/20] arm64: dts: Update cache properties for rockchip [19/20] arm64: dts: Update cache properties for synaptics [20/20] arm64: dts: Update cache properties for tesla

Commit Message

Pierre Gondois Oct. 31, 2022, 9:20 a.m. UTC

  The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes

The recently added init_of_cache_level() function checks
these properties. Add them if missing.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
 arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi      | 1 +
 arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
 arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
 arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
 4 files changed, 6 insertions(+)

Comments

Chris Packham Oct. 31, 2022, 8:12 p.m. UTC | #1

On 31/10/22 22:20, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

For ac5-98dx25xx.dtsi

Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

> ---
>   arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi      | 1 +
>   arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
>   arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
>   arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
>   4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>   
>   		l2: l2-cache {
>   			compatible = "cache";
> +			cache-level = <2>;
>   		};
>   	};
>   
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
>   			cache-size = <0x80000>;
>   			cache-line-size = <64>;
>   			cache-sets = <512>;
> +			cache-level = <2>;
>   		};
>   	};
>   
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>   			cache-size = <0x80000>;
>   			cache-line-size = <64>;
>   			cache-sets = <512>;
> +			cache-level = <2>;
>   		};
>   
>   		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>   			cache-size = <0x80000>;
>   			cache-line-size = <64>;
>   			cache-sets = <512>;
> +			cache-level = <2>;
>   		};
>   	};
>   };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>   			cache-size = <0x80000>;
>   			cache-line-size = <64>;
>   			cache-sets = <512>;
> +			cache-level = <2>;
>   		};
>   
>   		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>   			cache-size = <0x80000>;
>   			cache-line-size = <64>;
>   			cache-sets = <512>;
> +			cache-level = <2>;
>   		};
>   	};
>   };

Krzysztof Kozlowski Nov. 2, 2022, 8:47 p.m. UTC | #2

On 31/10/2022 05:20, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> 
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
> 
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Your threading is broken.

Best regards,
Krzysztof

Gregory CLEMENT Nov. 28, 2022, 12:09 a.m. UTC | #3

Pierre Gondois <pierre.gondois@arm.com> writes:

> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Applied on mvebu/dt64

Thanks,

Gregory
> ---
>  arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi      | 1 +
>  arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
>  arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
>  arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
>  4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>  
>  		l2: l2-cache {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  
>  		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  
>  		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  };
> -- 
> 2.25.1
>

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 80b44c7df56a..d4770acec6ac 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -49,6 +49,7 @@  cpu1: cpu@1 {
 
 		l2: l2-cache {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index fcab5173fe67..990f70303fe6 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -51,6 +51,7 @@  l2: l2-cache {
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 3db427122f9e..a7b8e001cc9c 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -81,6 +81,7 @@  l2_0: l2-cache0 {
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 
 		l2_1: l2-cache1 {
@@ -88,6 +89,7 @@  l2_1: l2-cache1 {
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 	};
 };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 68782f161f12..7740098fd108 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -81,6 +81,7 @@  l2_0: l2-cache0 {
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 
 		l2_1: l2-cache1 {
@@ -88,6 +89,7 @@  l2_1: l2-cache1 {
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 	};
 };