diff mbox series

[1/3] dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx

Message ID 20221121041757.418645-2-uwu@icenowy.me
State New
Headers
Series Some DT binding quirks for T-Head C9xx |

Commit Message

Icenowy Zheng Nov. 21, 2022, 4:17 a.m. UTC 
  T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
compliant to the newcoming ACLINT spec) because of lack of mtime
register.

Add a compatible string formatted like the C9xx-specific PLIC
compatible, and do not allow a SiFive one as fallback because they're
not really compliant.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Krzysztof Kozlowski Nov. 21, 2022, 10:06 a.m. UTC | #1 
On 21/11/2022 05:17, Icenowy Zheng wrote:
> T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> compliant to the newcoming ACLINT spec) because of lack of mtime
> register.
> 
> Add a compatible string formatted like the C9xx-specific PLIC
> compatible, and do not allow a SiFive one as fallback because they're
> not really compliant.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Samuel Holland Nov. 26, 2022, 7:39 p.m. UTC | #2 
On 11/20/22 22:17, Icenowy Zheng wrote:
> T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> compliant to the newcoming ACLINT spec) because of lack of mtime
> register.
> 
> Add a compatible string formatted like the C9xx-specific PLIC
> compatible, and do not allow a SiFive one as fallback because they're
> not really compliant.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)

Reviewed-by: Samuel Holland <samuel@sholland.org>
Icenowy Zheng Nov. 27, 2022, 7:25 a.m. UTC | #3 
在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道：
> T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> compliant to the newcoming ACLINT spec) because of lack of mtime
> register.
> 
> Add a compatible string formatted like the C9xx-specific PLIC
> compatible, and do not allow a SiFive one as fallback because they're
> not really compliant.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Could this patch get applied individually?

I want to drop the practice of the latter two patches and send new
RFCs, and this patch is a dependency of some OpenSBI patch.

> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8
> ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index bbad24165837..aada6957216c 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -20,6 +20,10 @@ description:
>    property of "/cpus" DT node. The "timebase-frequency" DT property
> is
>    described in Documentation/devicetree/bindings/riscv/cpus.yaml
>  
> +  T-Head C906/C910 CPU cores include an implementation of CLINT too,
> however
> +  their implementation lacks a memory-mapped MTIME register, thus
> not
> +  compatible with SiFive ones.
> +
>  properties:
>    compatible:
>      oneOf:
> @@ -29,6 +33,10 @@ properties:
>                - starfive,jh7100-clint
>                - canaan,k210-clint
>            - const: sifive,clint0
> +      - items:
> +          - enum:
> +              - allwinner,sun20i-d1-clint
> +          - const: thead,c900-clint
>        - items:
>            - const: sifive,clint0
>            - const: riscv,clint0
Icenowy Zheng Dec. 7, 2022, 10:47 a.m. UTC | #4 
在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道：
> T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> compliant to the newcoming ACLINT spec) because of lack of mtime
> register.
> 
> Add a compatible string formatted like the C9xx-specific PLIC
> compatible, and do not allow a SiFive one as fallback because they're
> not really compliant.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Hi, could this patch be picked ASAP? Becuase it will be used then in
further OpenSBI patches to enable proper operation of T-Head timer.

I know the following 2 patches are in doubt and further rework for them
are needed.

> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8
> ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index bbad24165837..aada6957216c 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -20,6 +20,10 @@ description:
>    property of "/cpus" DT node. The "timebase-frequency" DT property
> is
>    described in Documentation/devicetree/bindings/riscv/cpus.yaml
>  
> +  T-Head C906/C910 CPU cores include an implementation of CLINT too,
> however
> +  their implementation lacks a memory-mapped MTIME register, thus
> not
> +  compatible with SiFive ones.
> +
>  properties:
>    compatible:
>      oneOf:
> @@ -29,6 +33,10 @@ properties:
>                - starfive,jh7100-clint
>                - canaan,k210-clint
>            - const: sifive,clint0
> +      - items:
> +          - enum:
> +              - allwinner,sun20i-d1-clint
> +          - const: thead,c900-clint
>        - items:
>            - const: sifive,clint0
>            - const: riscv,clint0
Conor Dooley Dec. 7, 2022, 11:33 a.m. UTC | #5 
On Wed, Dec 07, 2022 at 06:47:26PM +0800, Icenowy Zheng wrote:
> 在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道：
> > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> > compliant to the newcoming ACLINT spec) because of lack of mtime
> > register.
> > 
> > Add a compatible string formatted like the C9xx-specific PLIC
> > compatible, and do not allow a SiFive one as fallback because they're
> > not really compliant.
> > 
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> 
> Hi, could this patch be picked ASAP? Becuase it will be used then in
> further OpenSBI patches to enable proper operation of T-Head timer.
> 
> I know the following 2 patches are in doubt and further rework for them
> are needed.

Since it's me that's asking the questions about the other patches, but
have no comments about this particular one:
Acked-by: Conor Dooley <conor.dooley@microchip.com>

HTH Icenowy!

> > ---
> >  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8
> > ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > index bbad24165837..aada6957216c 100644
> > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > @@ -20,6 +20,10 @@ description:
> >    property of "/cpus" DT node. The "timebase-frequency" DT property
> > is
> >    described in Documentation/devicetree/bindings/riscv/cpus.yaml
> >  
> > +  T-Head C906/C910 CPU cores include an implementation of CLINT too,
> > however
> > +  their implementation lacks a memory-mapped MTIME register, thus
> > not
> > +  compatible with SiFive ones.
> > +
> >  properties:
> >    compatible:
> >      oneOf:
> > @@ -29,6 +33,10 @@ properties:
> >                - starfive,jh7100-clint
> >                - canaan,k210-clint
> >            - const: sifive,clint0
> > +      - items:
> > +          - enum:
> > +              - allwinner,sun20i-d1-clint
> > +          - const: thead,c900-clint
> >        - items:
> >            - const: sifive,clint0
> >            - const: riscv,clint0
> 
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index bbad24165837..aada6957216c 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -20,6 +20,10 @@  description:
   property of "/cpus" DT node. The "timebase-frequency" DT property is
   described in Documentation/devicetree/bindings/riscv/cpus.yaml
 
+  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
+  their implementation lacks a memory-mapped MTIME register, thus not
+  compatible with SiFive ones.
+
 properties:
   compatible:
     oneOf:
@@ -29,6 +33,10 @@  properties:
               - starfive,jh7100-clint
               - canaan,k210-clint
           - const: sifive,clint0
+      - items:
+          - enum:
+              - allwinner,sun20i-d1-clint
+          - const: thead,c900-clint
       - items:
           - const: sifive,clint0
           - const: riscv,clint0