diff mbox series

[4/5] RISC-V: Remove integer vector eqne pattern

Message ID 20240301062711.207137-5-demin.han@starfivetech.com
State Unresolved
Headers
Series RISC-V: Support vf and vx for autovec comparison of |

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Commit Message

demin.han March 1, 2024, 6:27 a.m. UTC 
  We can unify eqne and other comparison operations.

Tested on RV32 and RV64.

gcc/ChangeLog:

	* config/riscv/predicates.md (comparison_except_eqge_operator): Only
      exclue ge
	(comparison_except_ge_operator): Ditto
	* config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern
	(expand_strcmp): Ditto
	* config/riscv/riscv-vector-builtins-bases.cc: Remvoe eqne cond
	* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove eqne
      patterns
	(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
	(*pred_eqne<mode>_scalar): Ditto
	(*pred_eqne<mode>_scalar_narrow): Ditto
	(*pred_eqne<mode>_extended_scalar_merge_tie_mask): Ditto
	(*pred_eqne<mode>_extended_scalar): Ditto
	(*pred_eqne<mode>_extended_scalar_narrow): Ditto

Signed-off-by: demin.han <demin.han@starfivetech.com>
---
 gcc/config/riscv/predicates.md                |   4 +-
 gcc/config/riscv/riscv-string.cc              |   4 +-
 .../riscv/riscv-vector-builtins-bases.cc      |   3 -
 gcc/config/riscv/vector.md                    | 279 +-----------------
 4 files changed, 15 insertions(+), 275 deletions(-)

Comments

juzhe.zhong@rivai.ai March 1, 2024, 7:37 a.m. UTC | #1 
Hi, han. My review comment of this patch is same as I said in:



[PATCH 1/5] RISC-V: Remove float vector eqne pattern

&nbsp;
&nbsp;
------------------&nbsp;Original&nbsp;------------------
From: &nbsp;"demin.han"<demin.han@starfivetech.com&gt;;
Date: &nbsp;Fri, Mar 1, 2024 02:27 PM
To: &nbsp;"gcc-patches"<gcc-patches@gcc.gnu.org&gt;; 
Cc: &nbsp;"juzhe.zhong"<juzhe.zhong@rivai.ai&gt;; "kito.cheng"<kito.cheng@gmail.com&gt;; "Li, Pan2"<pan2.li@intel.com&gt;; "jeffreyalaw"<jeffreyalaw@gmail.com&gt;; 
Subject: &nbsp;[PATCH 4/5] RISC-V: Remove integer vector eqne pattern

&nbsp;

We can unify eqne and other comparison operations.

Tested on RV32 and RV64.

gcc/ChangeLog:

	* config/riscv/predicates.md (comparison_except_eqge_operator): Only
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; exclue ge
	(comparison_except_ge_operator): Ditto
	* config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern
	(expand_strcmp): Ditto
	* config/riscv/riscv-vector-builtins-bases.cc: Remvoe eqne cond
	* config/riscv/vector.md (@pred_eqne<mode&gt;_scalar): Remove eqne
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; patterns
	(*pred_eqne<mode&gt;_scalar_merge_tie_mask): Ditto
	(*pred_eqne<mode&gt;_scalar): Ditto
	(*pred_eqne<mode&gt;_scalar_narrow): Ditto
	(*pred_eqne<mode&gt;_extended_scalar_merge_tie_mask): Ditto
	(*pred_eqne<mode&gt;_extended_scalar): Ditto
	(*pred_eqne<mode&gt;_extended_scalar_narrow): Ditto

Signed-off-by: demin.han <demin.han@starfivetech.com&gt;
---
&nbsp;gcc/config/riscv/predicates.md&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp; 4 +-
&nbsp;gcc/config/riscv/riscv-string.cc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp; 4 +-
&nbsp;.../riscv/riscv-vector-builtins-bases.cc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp; 3 -
&nbsp;gcc/config/riscv/vector.md&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 279 +-----------------
&nbsp;4 files changed, 15 insertions(+), 275 deletions(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 6c87a7bd1f4..7f144551bb2 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -548,8 +548,8 @@ (define_predicate "ltge_operator"
&nbsp;(define_predicate "comparison_except_ltge_operator"
&nbsp;&nbsp; (match_code "eq,ne,le,leu,gt,gtu"))
&nbsp;
-(define_predicate "comparison_except_eqge_operator"
-&nbsp; (match_code "le,leu,gt,gtu,lt,ltu"))
+(define_predicate "comparison_except_ge_operator"
+&nbsp; (match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
&nbsp;
&nbsp;(define_predicate "ge_operator"
&nbsp;&nbsp; (match_code "ge,geu"))
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index b09b51d7526..da33bd74ac6 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -1074,7 +1074,7 @@ expand_rawmemchr (machine_mode mode, rtx dst, rtx haystack, rtx needle,
&nbsp;&nbsp; /* Compare needle with haystack and store in a mask.&nbsp; */
&nbsp;&nbsp; rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec);
&nbsp;&nbsp; rtx vmsops[] = {mask, eq, vec, needle};
-&nbsp; emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+&nbsp; emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
&nbsp;		&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; riscv_vector::COMPARE_OP, vmsops, cnt);
&nbsp;
&nbsp;&nbsp; /* Find the first bit in the mask.&nbsp; */
@@ -1200,7 +1200,7 @@ expand_strcmp (rtx result, rtx src1, rtx src2, rtx nbytes,
&nbsp;&nbsp;&nbsp;&nbsp; = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, CONST0_RTX (mode)),
&nbsp;		&nbsp; vec1);
&nbsp;&nbsp; rtx vmsops1[] = {mask0, eq0, vec1, CONST0_RTX (mode)};
-&nbsp; emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+&nbsp; emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
&nbsp;		&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; riscv_vector::COMPARE_OP, vmsops1, cnt);
&nbsp;
&nbsp;&nbsp; /* Look for vec1 != vec2 (includes vec2[i] == 0).&nbsp; */
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d414721ede8..0cef0b91758 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -718,9 +718,6 @@ public:
&nbsp;	&nbsp; if (CODE == GE || CODE == GEU)
&nbsp;	&nbsp;&nbsp;&nbsp; return e.use_compare_insn (CODE, code_for_pred_ge_scalar (
&nbsp;					&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; e.vector_mode ()));
-	&nbsp; else if (CODE == EQ || CODE == NE)
-	&nbsp;&nbsp;&nbsp; return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
-					&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; e.vector_mode ()));
&nbsp;	&nbsp; else
&nbsp;	&nbsp;&nbsp;&nbsp; return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
&nbsp;					&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; e.vector_mode ()));
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 9210d7c28ad..544ca4af938 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4671,7 +4671,7 @@ (define_expand "@pred_cmp<mode&gt;_scalar"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_QHS 4 "register_operand")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_QHS
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"))])
@@ -4689,7 +4689,7 @@ (define_insn "*pred_cmp<mode&gt;_scalar_merge_tie_mask"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 2 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 2 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_QHS 3 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_QHS
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; r"))])
@@ -4714,7 +4714,7 @@ (define_insn "*pred_cmp<mode&gt;_scalar"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_QHS 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_QHS
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))])
@@ -4736,7 +4736,7 @@ (define_insn "*pred_cmp<mode&gt;_scalar_narrow"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_QHS 4 "register_operand"&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_QHS
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))])
@@ -4747,92 +4747,6 @@ (define_insn "*pred_cmp<mode&gt;_scalar_narrow"
&nbsp;&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
&nbsp;&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
&nbsp;
-(define_expand "@pred_eqne<mode&gt;_scalar"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_QHS
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_QHS 4 "register_operand")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand")))]
-&nbsp; "TARGET_VECTOR"
-&nbsp; {})
-
-(define_insn "*pred_eqne<mode&gt;_scalar_merge_tie_mask"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; 0")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 5 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 2 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_QHS
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; r"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_QHS 3 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " vr")])
-	&nbsp; (match_dup 1)))]
-&nbsp; "TARGET_VECTOR"
-&nbsp; "vms%B2.vx\t%0,%3,%4,v0.t"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "merge_op_idx" "1")
-&nbsp;&nbsp; (set_attr "vl_op_idx" "5")
-&nbsp;&nbsp; (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-&nbsp;&nbsp; (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode&gt;_scalar"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; &amp;vr,&nbsp;&nbsp; &amp;vr")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "vmWc1,vmWc1,vmWc1,vmWc1")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_QHS
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_QHS 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_le_one (<MODE&gt;mode)"
-&nbsp; "vms%B3.vx\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL &gt; dest LMUL.
-(define_insn "*pred_eqne<mode&gt;_scalar_narrow"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp; &amp;vr,&nbsp; &amp;vr")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; 0,vmWc1,vmWc1,vmWc1,vmWc1")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_QHS
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_QHS 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vu,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_gt_one (<MODE&gt;mode)"
-&nbsp; "vms%B3.vx\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
&nbsp;;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
&nbsp;;; we need to deal with SEW = 64 in RV32 system.
&nbsp;(define_expand "@pred_cmp<mode&gt;_scalar"
@@ -4845,7 +4759,7 @@ (define_expand "@pred_cmp<mode&gt;_scalar"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_D 4 "register_operand")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_D
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "reg_or_int_operand"))])
@@ -4875,39 +4789,6 @@ (define_expand "@pred_cmp<mode&gt;_scalar"
&nbsp;&nbsp;&nbsp;&nbsp; DONE;
&nbsp;})
&nbsp;
-(define_expand "@pred_eqne<mode&gt;_scalar"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_D
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "reg_or_int_operand"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_D 4 "register_operand")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand")))]
-&nbsp; "TARGET_VECTOR"
-{
-&nbsp; enum rtx_code code = GET_CODE (operands[3]);
-&nbsp; if (riscv_vector::sew64_scalar_helper (
-	operands,
-	/* scalar op */&amp;operands[5],
-	/* vl */operands[6],
-	<MODE&gt;mode,
-	riscv_vector::has_vi_variant_p (code, operands[5]),
-	[] (rtx *operands, rtx boardcast_scalar) {
-	&nbsp; emit_insn (gen_pred_cmp<mode&gt; (operands[0], operands[1],
-	&nbsp; 	operands[2], operands[3], operands[4], boardcast_scalar,
-		operands[6], operands[7], operands[8]));
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; },
-	(riscv_vector::avl_type) INTVAL (operands[8])))
-&nbsp;&nbsp;&nbsp; DONE;
-})
-
&nbsp;(define_insn "*pred_cmp<mode&gt;_scalar_merge_tie_mask"
&nbsp;&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm")
&nbsp;	(if_then_else:<VM&gt;
@@ -4918,7 +4799,7 @@ (define_insn "*pred_cmp<mode&gt;_scalar_merge_tie_mask"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 2 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 2 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_D 3 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_D
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; r"))])
@@ -4932,30 +4813,6 @@ (define_insn "*pred_cmp<mode&gt;_scalar_merge_tie_mask"
&nbsp;&nbsp;&nbsp; (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
&nbsp;&nbsp;&nbsp; (set (attr "avl_type_idx") (const_int 7))])
&nbsp;
-(define_insn "*pred_eqne<mode&gt;_scalar_merge_tie_mask"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; 0")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 5 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 2 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_D
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; r"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_D 3 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " vr")])
-	&nbsp; (match_dup 1)))]
-&nbsp; "TARGET_VECTOR"
-&nbsp; "vms%B2.vx\t%0,%3,%4,v0.t"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "merge_op_idx" "1")
-&nbsp;&nbsp; (set_attr "vl_op_idx" "5")
-&nbsp;&nbsp; (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-&nbsp;&nbsp; (set (attr "avl_type_idx") (const_int 7))])
-
&nbsp;;; We don't use early-clobber for LMUL <= 1 to get better codegen.
&nbsp;(define_insn "*pred_cmp<mode&gt;_scalar"
&nbsp;&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; &amp;vr,&nbsp;&nbsp; &amp;vr")
@@ -4967,7 +4824,7 @@ (define_insn "*pred_cmp<mode&gt;_scalar"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_D
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))])
@@ -4989,7 +4846,7 @@ (define_insn "*pred_cmp<mode&gt;_scalar_narrow"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_D
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))])
@@ -5000,50 +4857,6 @@ (define_insn "*pred_cmp<mode&gt;_scalar_narrow"
&nbsp;&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
&nbsp;&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
&nbsp;
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode&gt;_scalar"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; &amp;vr,&nbsp;&nbsp; &amp;vr")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "vmWc1,vmWc1,vmWc1,vmWc1")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_D
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_le_one (<MODE&gt;mode)"
-&nbsp; "vms%B3.vx\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL &gt; dest LMUL.
-(define_insn "*pred_eqne<mode&gt;_scalar_narrow"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp; &amp;vr,&nbsp; &amp;vr")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; 0,vmWc1,vmWc1,vmWc1,vmWc1")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_D
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r"))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vu,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_gt_one (<MODE&gt;mode)"
-&nbsp; "vms%B3.vx\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
&nbsp;(define_insn "*pred_cmp<mode&gt;_extended_scalar_merge_tie_mask"
&nbsp;&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm")
&nbsp;	(if_then_else:<VM&gt;
@@ -5054,7 +4867,7 @@ (define_insn "*pred_cmp<mode&gt;_extended_scalar_merge_tie_mask"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 2 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 2 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_D 3 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_D
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (sign_extend:<VEL&gt;
@@ -5080,7 +4893,7 @@ (define_insn "*pred_cmp<mode&gt;_extended_scalar"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_D
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (sign_extend:<VEL&gt;
@@ -5102,7 +4915,7 @@ (define_insn "*pred_cmp<mode&gt;_extended_scalar_narrow"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_eqge_operator"
+	&nbsp; (match_operator:<VM&gt; 3 "comparison_except_ge_operator"
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp; [(match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_duplicate:V_VLSI_D
&nbsp;	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (sign_extend:<VEL&gt;
@@ -5114,76 +4927,6 @@ (define_insn "*pred_cmp<mode&gt;_extended_scalar_narrow"
&nbsp;&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
&nbsp;&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
&nbsp;
-(define_insn "*pred_eqne<mode&gt;_extended_scalar_merge_tie_mask"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; 0")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 5 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 2 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_D
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (sign_extend:<VEL&gt;
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VSUBEL&gt; 4 "register_operand"&nbsp;&nbsp; "&nbsp; r")))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_D 3 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " vr")])
-	&nbsp; (match_dup 1)))]
-&nbsp; "TARGET_VECTOR &amp;&amp; !TARGET_64BIT"
-&nbsp; "vms%B2.vx\t%0,%3,%4,v0.t"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "merge_op_idx" "1")
-&nbsp;&nbsp; (set_attr "vl_op_idx" "5")
-&nbsp;&nbsp; (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-&nbsp;&nbsp; (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode&gt;_extended_scalar"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; &amp;vr,&nbsp;&nbsp; &amp;vr")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "vmWc1,vmWc1,vmWc1,vmWc1")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_D
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (sign_extend:<VEL&gt;
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VSUBEL&gt; 5 "register_operand" "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r")))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_le_one (<MODE&gt;mode) &amp;&amp; !TARGET_64BIT"
-&nbsp; "vms%B3.vx\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-(define_insn "*pred_eqne<mode&gt;_extended_scalar_narrow"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "=vm,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp; &amp;vr,&nbsp; &amp;vr")
-	(if_then_else:<VM&gt;
-	&nbsp; (unspec:<VM&gt;
-	&nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; 0,vmWc1,vmWc1,vmWc1,vmWc1")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-	&nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	&nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-	&nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSI_D
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (sign_extend:<VEL&gt;
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VSUBEL&gt; 5 "register_operand" "&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r,&nbsp;&nbsp;&nbsp; r")))
-	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSI_D 4 "register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-	&nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vu,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_gt_one (<MODE&gt;mode) &amp;&amp; !TARGET_64BIT"
-&nbsp; "vms%B3.vx\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vicmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
&nbsp;;; GE, vmsge.vx/vmsgeu.vx
&nbsp;;;
&nbsp;;; unmasked va &gt;= x
-- 
2.43.2
diff mbox series

Patch

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 6c87a7bd1f4..7f144551bb2 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -548,8 +548,8 @@  (define_predicate "ltge_operator"
 (define_predicate "comparison_except_ltge_operator"
   (match_code "eq,ne,le,leu,gt,gtu"))
 
-(define_predicate "comparison_except_eqge_operator"
-  (match_code "le,leu,gt,gtu,lt,ltu"))
+(define_predicate "comparison_except_ge_operator"
+  (match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
 
 (define_predicate "ge_operator"
   (match_code "ge,geu"))
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index b09b51d7526..da33bd74ac6 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -1074,7 +1074,7 @@  expand_rawmemchr (machine_mode mode, rtx dst, rtx haystack, rtx needle,
   /* Compare needle with haystack and store in a mask.  */
   rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec);
   rtx vmsops[] = {mask, eq, vec, needle};
-  emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+  emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
 		      riscv_vector::COMPARE_OP, vmsops, cnt);
 
   /* Find the first bit in the mask.  */
@@ -1200,7 +1200,7 @@  expand_strcmp (rtx result, rtx src1, rtx src2, rtx nbytes,
     = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, CONST0_RTX (mode)),
 		  vec1);
   rtx vmsops1[] = {mask0, eq0, vec1, CONST0_RTX (mode)};
-  emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+  emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
 		      riscv_vector::COMPARE_OP, vmsops1, cnt);
 
   /* Look for vec1 != vec2 (includes vec2[i] == 0).  */
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d414721ede8..0cef0b91758 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -718,9 +718,6 @@  public:
 	  if (CODE == GE || CODE == GEU)
 	    return e.use_compare_insn (CODE, code_for_pred_ge_scalar (
 					       e.vector_mode ()));
-	  else if (CODE == EQ || CODE == NE)
-	    return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
-					       e.vector_mode ()));
 	  else
 	    return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
 					       e.vector_mode ()));
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 9210d7c28ad..544ca4af938 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4671,7 +4671,7 @@  (define_expand "@pred_cmp<mode>_scalar"
 	     (match_operand 8 "const_int_operand")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_QHS 4 "register_operand")
 	      (vec_duplicate:V_VLSI_QHS
 	        (match_operand:<VEL> 5 "register_operand"))])
@@ -4689,7 +4689,7 @@  (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
 	     (match_operand 7 "const_int_operand"              "  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 2 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 2 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_QHS 3 "register_operand"       " vr")
 	      (vec_duplicate:V_VLSI_QHS
 	        (match_operand:<VEL> 4 "register_operand"      "  r"))])
@@ -4714,7 +4714,7 @@  (define_insn "*pred_cmp<mode>_scalar"
 	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,   vr,   vr,   vr")
 	      (vec_duplicate:V_VLSI_QHS
 	        (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r"))])
@@ -4736,7 +4736,7 @@  (define_insn "*pred_cmp<mode>_scalar_narrow"
 	     (match_operand 8 "const_int_operand"          "    i,    i,    i,    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_QHS 4 "register_operand"   "   vr,    0,    0,   vr,   vr")
 	      (vec_duplicate:V_VLSI_QHS
 	        (match_operand:<VEL> 5 "register_operand"  "    r,    r,    r,    r,    r"))])
@@ -4747,92 +4747,6 @@  (define_insn "*pred_cmp<mode>_scalar_narrow"
    (set_attr "mode" "<MODE>")
    (set_attr "spec_restriction" "none,thv,thv,none,none")])
 
-(define_expand "@pred_eqne<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand")
-	     (match_operand 6 "vector_length_operand")
-	     (match_operand 7 "const_int_operand")
-	     (match_operand 8 "const_int_operand")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_QHS
-	        (match_operand:<VEL> 5 "register_operand"))
-	      (match_operand:V_VLSI_QHS 4 "register_operand")])
-	  (match_operand:<VM> 2 "vector_merge_operand")))]
-  "TARGET_VECTOR"
-  {})
-
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vm")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "register_operand"           "  0")
-	     (match_operand 5 "vector_length_operand"           " rK")
-	     (match_operand 6 "const_int_operand"               "  i")
-	     (match_operand 7 "const_int_operand"               "  i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 2 "equality_operator"
-	     [(vec_duplicate:V_VLSI_QHS
-	        (match_operand:<VEL> 4 "register_operand"       "  r"))
-	      (match_operand:V_VLSI_QHS 3 "register_operand"        " vr")])
-	  (match_dup 1)))]
-  "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "merge_op_idx" "1")
-   (set_attr "vl_op_idx" "5")
-   (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-   (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vr,   vr,   &vr,   &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"         "   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"             "    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_QHS
-	        (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r"))
-	      (match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,   vr,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0,    vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vm,   vr,   vr,  &vr,  &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "    0,vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"         "   rK,   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"             "    i,    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_QHS
-	        (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r,    r"))
-	      (match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,    0,    0,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
 ;; we need to deal with SEW = 64 in RV32 system.
 (define_expand "@pred_cmp<mode>_scalar"
@@ -4845,7 +4759,7 @@  (define_expand "@pred_cmp<mode>_scalar"
 	     (match_operand 8 "const_int_operand")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_D 4 "register_operand")
 	      (vec_duplicate:V_VLSI_D
 	        (match_operand:<VEL> 5 "reg_or_int_operand"))])
@@ -4875,39 +4789,6 @@  (define_expand "@pred_cmp<mode>_scalar"
     DONE;
 })
 
-(define_expand "@pred_eqne<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand")
-	     (match_operand 6 "vector_length_operand")
-	     (match_operand 7 "const_int_operand")
-	     (match_operand 8 "const_int_operand")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_D
-	        (match_operand:<VEL> 5 "reg_or_int_operand"))
-	      (match_operand:V_VLSI_D 4 "register_operand")])
-	  (match_operand:<VM> 2 "vector_merge_operand")))]
-  "TARGET_VECTOR"
-{
-  enum rtx_code code = GET_CODE (operands[3]);
-  if (riscv_vector::sew64_scalar_helper (
-	operands,
-	/* scalar op */&operands[5],
-	/* vl */operands[6],
-	<MODE>mode,
-	riscv_vector::has_vi_variant_p (code, operands[5]),
-	[] (rtx *operands, rtx boardcast_scalar) {
-	  emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
-	  	operands[2], operands[3], operands[4], boardcast_scalar,
-		operands[6], operands[7], operands[8]));
-        },
-	(riscv_vector::avl_type) INTVAL (operands[8])))
-    DONE;
-})
-
 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
   [(set (match_operand:<VM> 0 "register_operand"                "=vm")
 	(if_then_else:<VM>
@@ -4918,7 +4799,7 @@  (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
 	     (match_operand 7 "const_int_operand"               "  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 2 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 2 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_D 3 "register_operand"          " vr")
 	      (vec_duplicate:V_VLSI_D
 	        (match_operand:<VEL> 4 "register_operand"       "  r"))])
@@ -4932,30 +4813,6 @@  (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
    (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
    (set (attr "avl_type_idx") (const_int 7))])
 
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vm")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "register_operand"           "  0")
-	     (match_operand 5 "vector_length_operand"           " rK")
-	     (match_operand 6 "const_int_operand"               "  i")
-	     (match_operand 7 "const_int_operand"               "  i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 2 "equality_operator"
-	     [(vec_duplicate:V_VLSI_D
-	        (match_operand:<VEL> 4 "register_operand"       "  r"))
-	      (match_operand:V_VLSI_D 3 "register_operand"          " vr")])
-	  (match_dup 1)))]
-  "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "merge_op_idx" "1")
-   (set_attr "vl_op_idx" "5")
-   (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-   (set (attr "avl_type_idx") (const_int 7))])
-
 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
 (define_insn "*pred_cmp<mode>_scalar"
   [(set (match_operand:<VM> 0 "register_operand"                "=vr,   vr,   &vr,   &vr")
@@ -4967,7 +4824,7 @@  (define_insn "*pred_cmp<mode>_scalar"
 	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_D 4 "register_operand"        "   vr,   vr,   vr,   vr")
 	      (vec_duplicate:V_VLSI_D
 	        (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r"))])
@@ -4989,7 +4846,7 @@  (define_insn "*pred_cmp<mode>_scalar_narrow"
 	     (match_operand 8 "const_int_operand"          "    i,    i,    i,    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_D 4 "register_operand"     "   vr,    0,    0,   vr,   vr")
 	      (vec_duplicate:V_VLSI_D
 	        (match_operand:<VEL> 5 "register_operand"  "    r,    r,    r,    r,    r"))])
@@ -5000,50 +4857,6 @@  (define_insn "*pred_cmp<mode>_scalar_narrow"
    (set_attr "mode" "<MODE>")
    (set_attr "spec_restriction" "none,thv,thv,none,none")])
 
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vr,   vr,   &vr,   &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"         "   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"             "    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_D
-	        (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r"))
-	      (match_operand:V_VLSI_D 4 "register_operand"        "   vr,   vr,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0,    vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vm,   vr,   vr,  &vr,  &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "    0,vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"         "   rK,   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"             "    i,    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"             "    i,    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_D
-	        (match_operand:<VEL> 5 "register_operand"     "    r,    r,    r,    r,    r"))
-	      (match_operand:V_VLSI_D 4 "register_operand"        "   vr,    0,    0,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
 (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
   [(set (match_operand:<VM> 0 "register_operand"               "=vm")
 	(if_then_else:<VM>
@@ -5054,7 +4867,7 @@  (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
 	     (match_operand 7 "const_int_operand"              "  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 2 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 2 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_D 3 "register_operand"         " vr")
 	      (vec_duplicate:V_VLSI_D
 	        (sign_extend:<VEL>
@@ -5080,7 +4893,7 @@  (define_insn "*pred_cmp<mode>_extended_scalar"
 	     (match_operand 8 "const_int_operand"              "    i,    i,    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_D 4 "register_operand"         "   vr,   vr,   vr,   vr")
 	      (vec_duplicate:V_VLSI_D
 	        (sign_extend:<VEL>
@@ -5102,7 +4915,7 @@  (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
 	     (match_operand 8 "const_int_operand"              "    i,    i,    i,    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "comparison_except_eqge_operator"
+	  (match_operator:<VM> 3 "comparison_except_ge_operator"
 	     [(match_operand:V_VLSI_D 4 "register_operand"         "   vr,    0,    0,   vr,   vr")
 	      (vec_duplicate:V_VLSI_D
 	        (sign_extend:<VEL>
@@ -5114,76 +4927,6 @@  (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
    (set_attr "mode" "<MODE>")
    (set_attr "spec_restriction" "none,thv,thv,none,none")])
 
-(define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
-  [(set (match_operand:<VM> 0 "register_operand"                 "=vm")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "register_operand"            "  0")
-	     (match_operand 5 "vector_length_operand"            " rK")
-	     (match_operand 6 "const_int_operand"                "  i")
-	     (match_operand 7 "const_int_operand"                "  i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 2 "equality_operator"
-	     [(vec_duplicate:V_VLSI_D
-	        (sign_extend:<VEL>
-	          (match_operand:<VSUBEL> 4 "register_operand"   "  r")))
-	      (match_operand:V_VLSI_D 3 "register_operand"           " vr")])
-	  (match_dup 1)))]
-  "TARGET_VECTOR && !TARGET_64BIT"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "merge_op_idx" "1")
-   (set_attr "vl_op_idx" "5")
-   (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-   (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_extended_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"                 "=vr,   vr,   &vr,   &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"          "   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"              "    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"              "    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_D
-	        (sign_extend:<VEL>
-	          (match_operand:<VSUBEL> 5 "register_operand" "    r,    r,    r,    r")))
-	      (match_operand:V_VLSI_D 4 "register_operand"         "   vr,   vr,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"         "   vu,    0,    vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
-  "vms%B3.vx\t%0,%4,%5%p1"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-(define_insn "*pred_eqne<mode>_extended_scalar_narrow"
-  [(set (match_operand:<VM> 0 "register_operand"                "=vm,   vr,   vr,  &vr,  &vr")
-	(if_then_else:<VM>
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"       "    0,vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 6 "vector_length_operand"          "   rK,   rK,   rK,   rK,   rK")
-	     (match_operand 7 "const_int_operand"              "    i,    i,    i,    i,    i")
-	     (match_operand 8 "const_int_operand"              "    i,    i,    i,    i,    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operator:<VM> 3 "equality_operator"
-	     [(vec_duplicate:V_VLSI_D
-	        (sign_extend:<VEL>
-	          (match_operand:<VSUBEL> 5 "register_operand" "    r,    r,    r,    r,    r")))
-	      (match_operand:V_VLSI_D 4 "register_operand"         "   vr,    0,    0,   vr,   vr")])
-	  (match_operand:<VM> 2 "vector_merge_operand"         "   vu,   vu,    0,   vu,    0")))]
-  "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
-  "vms%B3.vx\t%0,%4,%5%p1"
-  [(set_attr "type" "vicmp")
-   (set_attr "mode" "<MODE>")
-   (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
 ;; GE, vmsge.vx/vmsgeu.vx
 ;;
 ;; unmasked va >= x