diff mbox series

[4/5] dt-bindings: fsl-dma: fsl-edma: add fsl,imx8ulp-edma compatible string

Message ID 20240227-8ulp_edma-v1-4-7fcfe1e265c2@nxp.com
State New
Headers
Series dmaengine: fsl-edma: add 8ulp support |

Commit Message

Frank Li Feb. 27, 2024, 5:21 p.m. UTC 
  From: Joy Zou <joy.zou@nxp.com>

Add the compatible string 'fsl,imx8ulp-edma' to support the i.MX8ulp's
eDMA, and modify the clock number.

Signed-off-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 .../devicetree/bindings/dma/fsl,edma.yaml          | 24 ++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Feb. 29, 2024, 9:49 a.m. UTC | #1 
On 27/02/2024 18:21, Frank Li wrote:
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: fsl,imx8ulp-edma
> +    then:
> +      properties:
> +        clock:
> +          maxItems: 33
> +        clock-names:
> +          items:
> +            - const: dma
> +            - pattern: "^CH[0-31]-clk$"
> +        interrupt-names: false
> +        interrupts:
> +          maxItems: 32
> +        "#dma-cells":
> +          const: 3

Why suddenly fsl,vf610-edma can have from 2 to 33 clocks? Constrain
properly the variants.

Best regards,
Krzysztof
Frank Li Feb. 29, 2024, 3:54 p.m. UTC | #2 
On Thu, Feb 29, 2024 at 10:49:43AM +0100, Krzysztof Kozlowski wrote:
> On 27/02/2024 18:21, Frank Li wrote:
> >  
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: fsl,imx8ulp-edma
> > +    then:
> > +      properties:
> > +        clock:
> > +          maxItems: 33
> > +        clock-names:
> > +          items:
> > +            - const: dma
> > +            - pattern: "^CH[0-31]-clk$"
> > +        interrupt-names: false
> > +        interrupts:
> > +          maxItems: 32
> > +        "#dma-cells":
> > +          const: 3
> 
> Why suddenly fsl,vf610-edma can have from 2 to 33 clocks? Constrain
> properly the variants.

Suppose you talk about 'fsl,imx8ulp-edma' instead 'fsl,vf610-edma'.

imx8ulp each channel have one clk, there are 32 channel. 1 channel for core
controller. So max became 32.

I can add above information in commit message.

> 
> Best regards,
> Krzysztof
>
Krzysztof Kozlowski Feb. 29, 2024, 3:58 p.m. UTC | #3 
On 29/02/2024 16:54, Frank Li wrote:
> On Thu, Feb 29, 2024 at 10:49:43AM +0100, Krzysztof Kozlowski wrote:
>> On 27/02/2024 18:21, Frank Li wrote:
>>>  
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: fsl,imx8ulp-edma
>>> +    then:
>>> +      properties:
>>> +        clock:
>>> +          maxItems: 33
>>> +        clock-names:
>>> +          items:
>>> +            - const: dma
>>> +            - pattern: "^CH[0-31]-clk$"
>>> +        interrupt-names: false
>>> +        interrupts:
>>> +          maxItems: 32
>>> +        "#dma-cells":
>>> +          const: 3
>>
>> Why suddenly fsl,vf610-edma can have from 2 to 33 clocks? Constrain
>> properly the variants.
> 
> Suppose you talk about 'fsl,imx8ulp-edma' instead 'fsl,vf610-edma'.
> 
> imx8ulp each channel have one clk, there are 32 channel. 1 channel for core
> controller. So max became 32.
> 
> I can add above information in commit message.

No, I meant Vybrid. Quick look at this code and the actual file suggest
that you allow vybrid with 30-whatever clocks. Test it.

Best regards,
Krzysztof
Frank Li Feb. 29, 2024, 4:03 p.m. UTC | #4 
On Thu, Feb 29, 2024 at 04:58:23PM +0100, Krzysztof Kozlowski wrote:
> On 29/02/2024 16:54, Frank Li wrote:
> > On Thu, Feb 29, 2024 at 10:49:43AM +0100, Krzysztof Kozlowski wrote:
> >> On 27/02/2024 18:21, Frank Li wrote:
> >>>  
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            const: fsl,imx8ulp-edma
> >>> +    then:
> >>> +      properties:
> >>> +        clock:
> >>> +          maxItems: 33
> >>> +        clock-names:
> >>> +          items:
> >>> +            - const: dma
> >>> +            - pattern: "^CH[0-31]-clk$"
> >>> +        interrupt-names: false
> >>> +        interrupts:
> >>> +          maxItems: 32
> >>> +        "#dma-cells":
> >>> +          const: 3
> >>
> >> Why suddenly fsl,vf610-edma can have from 2 to 33 clocks? Constrain
> >> properly the variants.
> > 
> > Suppose you talk about 'fsl,imx8ulp-edma' instead 'fsl,vf610-edma'.
> > 
> > imx8ulp each channel have one clk, there are 32 channel. 1 channel for core
> > controller. So max became 32.
> > 
> > I can add above information in commit message.
> 
> No, I meant Vybrid. Quick look at this code and the actual file suggest
> that you allow vybrid with 30-whatever clocks. Test it.

Any tools or good method to find it? 

Frank

> 
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
index aa51d278cb67b..6c04303dbe453 100644
--- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
+++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
@@ -23,6 +23,7 @@  properties:
           - fsl,imx7ulp-edma
           - fsl,imx8qm-adma
           - fsl,imx8qm-edma
+          - fsl,imx8ulp-edma
           - fsl,imx93-edma3
           - fsl,imx93-edma4
           - fsl,imx95-edma5
@@ -53,11 +54,11 @@  properties:
 
   clocks:
     minItems: 1
-    maxItems: 2
+    maxItems: 33
 
   clock-names:
     minItems: 1
-    maxItems: 2
+    maxItems: 33
 
   big-endian:
     description: |
@@ -151,6 +152,25 @@  allOf:
         dma-channels:
           const: 32
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8ulp-edma
+    then:
+      properties:
+        clock:
+          maxItems: 33
+        clock-names:
+          items:
+            - const: dma
+            - pattern: "^CH[0-31]-clk$"
+        interrupt-names: false
+        interrupts:
+          maxItems: 32
+        "#dma-cells":
+          const: 3
+
 unevaluatedProperties: false
 
 examples: