Message ID | 20240227003630.3634533-3-samuel.holland@sifive.com |
---|---|
State | New |
Headers |
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Mon, 26 Feb 2024 16:36:35 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id z25-20020a631919000000b005dc85821c80sm4504117pgl.12.2024.02.26.16.36.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Feb 2024 16:36:35 -0800 (PST) From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Samuel Holland <samuel.holland@sifive.com> Subject: [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM Date: Mon, 26 Feb 2024 16:34:47 -0800 Message-ID: <20240227003630.3634533-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227003630.3634533-1-samuel.holland@sifive.com> References: <20240227003630.3634533-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792010358072618943 X-GMAIL-MSGID: 1792010358072618943 |
Series |
riscv: 64-bit NOMMU fixes and enhancements
|
|
Commit Message
Samuel Holland
Feb. 27, 2024, 12:34 a.m. UTC
commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
mapping") added logic to allow using RAM below the kernel load address.
However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
kernel load address. Since that range of memory corresponds to PFNs
below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
mem_map and corrupts adjacent kernel memory. Fix this by restoring the
previous behavior for NOMMU kernels.
Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
arch/riscv/include/asm/page.h | 2 +-
arch/riscv/mm/init.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Comments
On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote: > commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear > mapping") added logic to allow using RAM below the kernel load address. > However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the > kernel load address. Since that range of memory corresponds to PFNs > below ARCH_PFN_OFFSET, mm initialization runs off the beginning of > mem_map and corrupts adjacent kernel memory. Fix this by restoring the > previous behavior for NOMMU kernels. > > Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping") This commit was a year ago, why has nobody reported this as being an issue before? > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> > --- > > arch/riscv/include/asm/page.h | 2 +- > arch/riscv/mm/init.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h > index 57e887bfa34c..94b3d6930fc3 100644 > --- a/arch/riscv/include/asm/page.h > +++ b/arch/riscv/include/asm/page.h > @@ -89,7 +89,7 @@ typedef struct page *pgtable_t; > #define PTE_FMT "%08lx" > #endif > > -#ifdef CONFIG_64BIT > +#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) > /* > * We override this value as its generic definition uses __pa too early in > * the boot process (before kernel_map.va_pa_offset is set). > diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c > index fa34cf55037b..0c00efc75643 100644 > --- a/arch/riscv/mm/init.c > +++ b/arch/riscv/mm/init.c > @@ -232,7 +232,7 @@ static void __init setup_bootmem(void) > * In 64-bit, any use of __va/__pa before this point is wrong as we > * did not know the start of DRAM before. > */ > - if (IS_ENABLED(CONFIG_64BIT)) > + if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU)) > kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base; > > /* > -- > 2.43.0 >
Hi Conor, On 2024-02-27 6:18 AM, Conor Dooley wrote: > On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote: >> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear >> mapping") added logic to allow using RAM below the kernel load address. >> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the >> kernel load address. Since that range of memory corresponds to PFNs >> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of >> mem_map and corrupts adjacent kernel memory. Fix this by restoring the >> previous behavior for NOMMU kernels. >> >> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping") > > This commit was a year ago, why has nobody reported this as being an > issue before? I can think of a few reasons: 1) NOMMU users are likely to be using RV32, which is not affected. 2) Before patch 4 of this series, NOMMU implied M-mode, so there was nothing in the way to prevent loading Linux at the very beginning of RAM. (U-Boot/SPL relocates itself to the end of RAM, so it would not cause a problem.) 3) Platforms where RAM does not begin at exactly 0x80000000 would be affected, there are several workarounds: change the start of RAM (for soft cores), change PAGE_OFFSET, or change the memory ranges in the devicetree to exclude anything below PAGE_OFFSET. It's possible that nobody was affected, but it's still technically a regression (a hypothetical platform with RAM from 0x40000000 to 0xc0000000 would crash instead of only being able to use half its RAM), so I thought it still deserved the Fixes: tag. Regards, Samuel >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >> --- >> >> arch/riscv/include/asm/page.h | 2 +- >> arch/riscv/mm/init.c | 2 +- >> 2 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h >> index 57e887bfa34c..94b3d6930fc3 100644 >> --- a/arch/riscv/include/asm/page.h >> +++ b/arch/riscv/include/asm/page.h >> @@ -89,7 +89,7 @@ typedef struct page *pgtable_t; >> #define PTE_FMT "%08lx" >> #endif >> >> -#ifdef CONFIG_64BIT >> +#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) >> /* >> * We override this value as its generic definition uses __pa too early in >> * the boot process (before kernel_map.va_pa_offset is set). >> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c >> index fa34cf55037b..0c00efc75643 100644 >> --- a/arch/riscv/mm/init.c >> +++ b/arch/riscv/mm/init.c >> @@ -232,7 +232,7 @@ static void __init setup_bootmem(void) >> * In 64-bit, any use of __va/__pa before this point is wrong as we >> * did not know the start of DRAM before. >> */ >> - if (IS_ENABLED(CONFIG_64BIT)) >> + if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU)) >> kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base; >> >> /* >> -- >> 2.43.0 >>
On Tue, Feb 27, 2024 at 01:22:12PM -0600, Samuel Holland wrote: > Hi Conor, > > On 2024-02-27 6:18 AM, Conor Dooley wrote: > > On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote: > >> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear > >> mapping") added logic to allow using RAM below the kernel load address. > >> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the > >> kernel load address. Since that range of memory corresponds to PFNs > >> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of > >> mem_map and corrupts adjacent kernel memory. Fix this by restoring the > >> previous behavior for NOMMU kernels. > >> > >> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping") > > > > This commit was a year ago, why has nobody reported this as being an > > issue before? > > I can think of a few reasons: > 1) NOMMU users are likely to be using RV32, which is not affected. > 2) Before patch 4 of this series, NOMMU implied M-mode, so there was nothing in > the way to prevent loading Linux at the very beginning of RAM. (U-Boot/SPL > relocates itself to the end of RAM, so it would not cause a problem.) > 3) Platforms where RAM does not begin at exactly 0x80000000 would be affected, > there are several workarounds: change the start of RAM (for soft cores), change > PAGE_OFFSET, or change the memory ranges in the devicetree to exclude anything > below PAGE_OFFSET. > > It's possible that nobody was affected, but it's still technically a regression > (a hypothetical platform with RAM from 0x40000000 to 0xc0000000 would crash > instead of only being able to use half its RAM), so I thought it still deserved > the Fixes: tag. Right, thanks for explaining. Cheers, Conor.
diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 57e887bfa34c..94b3d6930fc3 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -89,7 +89,7 @@ typedef struct page *pgtable_t; #define PTE_FMT "%08lx" #endif -#ifdef CONFIG_64BIT +#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) /* * We override this value as its generic definition uses __pa too early in * the boot process (before kernel_map.va_pa_offset is set). diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index fa34cf55037b..0c00efc75643 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -232,7 +232,7 @@ static void __init setup_bootmem(void) * In 64-bit, any use of __va/__pa before this point is wrong as we * did not know the start of DRAM before. */ - if (IS_ENABLED(CONFIG_64BIT)) + if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU)) kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base; /*