Message ID | 20240222183933.953C8BFF@davehans-spike.ostc.intel.com |
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State | New |
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Series |
x86: Rework system-wide configuration masquerading as per-cpu data
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Commit Message
Dave Hansen
Feb. 22, 2024, 6:39 p.m. UTC
From: Dave Hansen <dave.hansen@linux.intel.com> This is one of the few references to the per-cpu version of ->x86_phys_bits. It is theoretically possible to have this value vary from CPU to CPU. But in practice nobody builds systems that way. Continue outputting the value in /proc, but read it from the global configuration. Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> --- b/arch/x86/kernel/cpu/proc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On Thu, 2024-02-22 at 10:39 -0800, Dave Hansen wrote: > From: Dave Hansen <dave.hansen@linux.intel.com> > > This is one of the few references to the per-cpu version of > ->x86_phys_bits. It is theoretically possible to have this value vary > from CPU to CPU. But in practice nobody builds systems that way. > > Continue outputting the value in /proc, but read it from the global > configuration. > > Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> > --- > Reviewed-by: Kai Huang <kai.huang@intel.com>
diff -puN arch/x86/kernel/cpu/proc.c~proc-global-x86-phys-bits arch/x86/kernel/cpu/proc.c --- a/arch/x86/kernel/cpu/proc.c~proc-global-x86-phys-bits 2024-02-22 10:08:50.584536732 -0800 +++ b/arch/x86/kernel/cpu/proc.c 2024-02-22 10:08:50.584536732 -0800 @@ -133,7 +133,7 @@ static int show_cpuinfo(struct seq_file seq_printf(m, "clflush size\t: %u\n", c->x86_clflush_size); seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment); seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", - c->x86_phys_bits, c->x86_virt_bits); + x86_phys_bits(), c->x86_virt_bits); seq_puts(m, "power management:"); for (i = 0; i < 32; i++) {