diff mbox series

[v7,5/5] PCI: j721e: add j784s4 PCIe configuration

Message ID 20221124081221.1206167-6-mranostay@ti.com
State New
Headers
Series PCI: add 4x lane support for pci-j721e controllers |

Commit Message

Matt Ranostay Nov. 24, 2022, 8:12 a.m. UTC 
  Add PCIe configuration for j784s4 platform which has 4x lane support.

Tested-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Roger Quadros Nov. 25, 2022, 12:32 p.m. UTC | #1 
On 24/11/2022 10:12, Matt Ranostay wrote:
> Add PCIe configuration for j784s4 platform which has 4x lane support.
> 
> Tested-by: Achal Verma <a-verma1@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>

Reviewed-by: Roger Quadros <rogerq@kernel.org>

> ---
>  drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index dab3db9be6d8..c484d658c18a 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -330,6 +330,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
>  	.max_lanes = 1,
>  };
>  
> +static const struct j721e_pcie_data j784s4_pcie_rc_data = {
> +	.mode = PCI_MODE_RC,
> +	.quirk_retrain_flag = true,
> +	.is_intc_v1 = true,
> +	.byte_access_allowed = false,
> +	.linkdown_irq_regfield = LINK_DOWN,
> +	.max_lanes = 4,
> +};
> +
> +static const struct j721e_pcie_data j784s4_pcie_ep_data = {
> +	.mode = PCI_MODE_EP,
> +	.linkdown_irq_regfield = LINK_DOWN,
> +	.max_lanes = 4,
> +};
> +
>  static const struct of_device_id of_j721e_pcie_match[] = {
>  	{
>  		.compatible = "ti,j721e-pcie-host",
> @@ -355,6 +370,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
>  		.compatible = "ti,am64-pcie-ep",
>  		.data = &am64_pcie_ep_data,
>  	},
> +	{
> +		.compatible = "ti,j784s4-pcie-host",
> +		.data = &j784s4_pcie_rc_data,
> +	},
> +	{
> +		.compatible = "ti,j784s4-pcie-ep",
> +		.data = &j784s4_pcie_ep_data,
> +	},
>  	{},
>  };
>  

--
cheers,
-roger
kernel test robot Nov. 25, 2022, 8:08 p.m. UTC | #2 
Hi Matt,

I love your patch! Yet something to improve:

[auto build test ERROR on helgaas-pci/next]
[also build test ERROR on next-20221125]
[cannot apply to helgaas-pci/for-linus linus/master v6.1-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Matt-Ranostay/PCI-add-4x-lane-support-for-pci-j721e-controllers/20221124-161712
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
patch link:    https://lore.kernel.org/r/20221124081221.1206167-6-mranostay%40ti.com
patch subject: [PATCH v7 5/5] PCI: j721e: add j784s4 PCIe configuration
config: i386-randconfig-a015
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/ee3fcfcf1caaa25a9ba8ccceaf917e0bd43c38a4
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Matt-Ranostay/PCI-add-4x-lane-support-for-pci-j721e-controllers/20221124-161712
        git checkout ee3fcfcf1caaa25a9ba8ccceaf917e0bd43c38a4
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/pci/controller/cadence/pci-j721e.c:336:3: error: field designator 'is_intc_v1' does not refer to any field in type 'const struct j721e_pcie_data'
           .is_intc_v1 = true,
            ^
   1 error generated.


vim +336 drivers/pci/controller/cadence/pci-j721e.c

   332	
   333	static const struct j721e_pcie_data j784s4_pcie_rc_data = {
   334		.mode = PCI_MODE_RC,
   335		.quirk_retrain_flag = true,
 > 336		.is_intc_v1 = true,
   337		.byte_access_allowed = false,
   338		.linkdown_irq_regfield = LINK_DOWN,
   339		.max_lanes = 4,
   340	};
   341
diff mbox series

Patch

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index dab3db9be6d8..c484d658c18a 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -330,6 +330,21 @@  static const struct j721e_pcie_data am64_pcie_ep_data = {
 	.max_lanes = 1,
 };
 
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+	.mode = PCI_MODE_RC,
+	.quirk_retrain_flag = true,
+	.is_intc_v1 = true,
+	.byte_access_allowed = false,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+	.mode = PCI_MODE_EP,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
 static const struct of_device_id of_j721e_pcie_match[] = {
 	{
 		.compatible = "ti,j721e-pcie-host",
@@ -355,6 +370,14 @@  static const struct of_device_id of_j721e_pcie_match[] = {
 		.compatible = "ti,am64-pcie-ep",
 		.data = &am64_pcie_ep_data,
 	},
+	{
+		.compatible = "ti,j784s4-pcie-host",
+		.data = &j784s4_pcie_rc_data,
+	},
+	{
+		.compatible = "ti,j784s4-pcie-ep",
+		.data = &j784s4_pcie_ep_data,
+	},
 	{},
 };