Message ID | 20240219160912.1206647-3-prabhakar.mahadev-lad.rj@bp.renesas.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-71645-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1382434dyc; Mon, 19 Feb 2024 08:10:55 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUOoBd6JLHf9+BNDGkFrHkEmhWBbdS1t1MOIJvL7JwqSJIHST7/2fyOac83KTUDJFFiiOfZalKFagGudTo7nvARtBdgwQ== X-Google-Smtp-Source: AGHT+IED42XnSwMQRUNu8Kd/4xtesZlFfusqAVzAdwTRi4v3z2lxzpHANxAnmbrIbkfUVuy986hQ X-Received: by 2002:a05:6e02:cd3:b0:365:224b:e601 with SMTP id c19-20020a056e020cd300b00365224be601mr5880410ilj.2.1708359055227; Mon, 19 Feb 2024 08:10:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708359055; cv=pass; d=google.com; s=arc-20160816; b=kF/ZoYG5P27Py7wZLR03hoOPh8i+p4tT7+bfb2+tIfAHnTpuCLnj70DaNw7HSCC5P+ x0haPyJwunswWY2lc+ULaD6cDFwph+gNYIh/WRlLBryf2jMpDJ0yYmFqEKkXhwIvX02Q VRSB6PEyCqu5nbdzpCccb+oo+JSD7Yiv0ZyEJAw/4Ts6y3ySoDnlf4rmbjUi7JlUQNH4 RqA+1k4t2t/YlPCKWC1jXxjgoOuUd560xnDzVAy6BCPqAU55pI2kSPemtbyylyDEgY2I 3tx0LEmX9tIug2C5vvFwIH2vd2e8bapgGkCK0IkYwWeLql5FupmdIplRs+9o0E6K+n2W A8Rw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Xh9vUfoHPZFnPPcTVso6vUO3bMJmWkfyYVswHNjvUxU=; fh=sSorVHY9LUi3pHeASTCQeqFFcthHJcpzzZRjaGggJ/I=; b=D9x8NB71NSyzhcBLa812vwlT1T5QgZBLVnZqNcKTb9dIiqANyMhmNl6JA36nC6K7w+ jb0hdE5f3GVnaZulmBqO9ynQVGDWKjjgEBZKHJO5kNhXD1tGaRV7cFV+4LSZ80V8ND6K zXGXe2jrbIhHrmTMXM4T3K1yhSvVEbeLMW6Pd7ijhp7EDy8+6wlllDuJt/5KKgEKcivd hODZYGFtla+11UBkRMfp67lx901yJRCbhMHxZutulgUxAwk4cvn/KbrMmBSvYRpHHTSK sG/lSCtFw8husbHxZ4vrRXUiBTAm1lu4MK4bjYHN5pX1/LSuapXTG6fY26OjD1OVqtJ2 lMGQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=Du7nmEJu; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-71645-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-71645-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id z25-20020a637e19000000b005d7b75a5df9si4686057pgc.669.2024.02.19.08.10.55 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 08:10:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-71645-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=Du7nmEJu; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-71645-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-71645-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id DF5E2282790 for <ouuuleilei@gmail.com>; Mon, 19 Feb 2024 16:10:54 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F3E673FB37; Mon, 19 Feb 2024 16:09:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Du7nmEJu" Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 294BD3B79D; Mon, 19 Feb 2024 16:09:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708358996; cv=none; b=Na6MmTjHIO28IvstGC6cFxbDUogfcOP8QHTqvOlaICEXULDFG5l1HPjEEJZoN/q6fezXmJIX39a6jio+Jhdq2q+oxJExfQti5Ddtef7NCMMlE+e9FQnLV1XAKXGUzHdc+yYoEfwm+FdXQgpaJoOvdGapkdQumoazhj5MRnmVAEM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708358996; c=relaxed/simple; bh=W9dB3rUMqoNAamOHOS2WOxt7HyATzwndZgN7uhrewD8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AJw9Cu7hw2EiRZsgH6Rt7v30V3A/FUoldlua9zR827y0g1oJU96d057T3DOVDPUnvTU7c91KGFMRhLO/TA2Xa3H1bvPEGKbe+MIq/22E6gNCm2/Ar7jECHES7ycpUo9GnS0fll7/I5U3nVKsrnfrNC+i3XMUgXy4vI+JslLiTVg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Du7nmEJu; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4126ac0c32eso3301445e9.1; Mon, 19 Feb 2024 08:09:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708358993; x=1708963793; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xh9vUfoHPZFnPPcTVso6vUO3bMJmWkfyYVswHNjvUxU=; b=Du7nmEJuUPfY+iSQAsc/JcdIzf7uBi16Y/Tl5VYVARFnn/R7LyqV5QdpqxtT7hZoDt WfS/VoGDzEJMVswns3L68hT2GxdbpRytN+EycOiYr6L4sglwr2XO8iamYfFAOGBzEQb1 2HnzHz9cO7mKTZXTW/zruOoy35thyyRUx2c3XTNoYyTcRQQ46rZTzywGtpMzmJtvaroj mfOoywzF4JCw64aYw6Jp5YReWDmVqcvWebjkC6+MJHgTPZKTCMARqBK+GvUCSD3jAGf5 CrAw2XbUkewCf5MsSluyAgcGkXIEJjehOaQ2o6V1XqZTas/bTb4U6MPvwmKcN40DcmfD q0yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708358993; x=1708963793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xh9vUfoHPZFnPPcTVso6vUO3bMJmWkfyYVswHNjvUxU=; b=rO9N4+AMvHvlXnQGt9wicbxVlR7sh5kDkXbRE+OWvkPA5wv8oJglNkO/CubNmwkAXf dRlaWbuFtnTma8jGSF6/wBJN5+Z1tpxe/7FuV7QzNV4Z4a/V4KfTOOj2JIP/a6rBxncG QCb81aJbqifu+S06wNWCzl8WsznUZxuugAISVBlDJnVIkpfA7Py2cUw483tySn9ateHo HLdob3XM3j6xDlvg5PiAIdpT+VUPLAdPatrT6h3Y1ScgYLGHj9y82QwzmvGegrevk2h6 SMQ2FspeUz25g7ICrIcKCCovEFSXAXKpj6YcNrfKjL8QFByR7oIKgMzl8+HPju+iLWeX 1JNA== X-Forwarded-Encrypted: i=1; AJvYcCVKYznC4rULt5G1Xky2gQbZwDctwjxHVvYY23DqoiA7+ofmeRiaW449AjfvFL9fi7lFWm9kue2sqzHroMkjYc57X4eDrMqoenyZ4TVCSZngvianKWkyiK19PaVbajo4IDU9X3qYqYISkdJfYctMruuGINAxXzckcg2Hqp6Sb6R0BJpzUNZpXpRiZZsP X-Gm-Message-State: AOJu0YzpPK7bz02w11TLPD0+LHpvE1Kw2LIt7t5eUkwf0IzUWZfbITRH c5Jc+0D6XvaZIdggFmTbAR5bw+qatD62kQBmigiOety3D/+7GV/XGSaTTi/Q X-Received: by 2002:a05:600c:1396:b0:411:d889:f3cd with SMTP id u22-20020a05600c139600b00411d889f3cdmr8958674wmf.34.1708358993362; Mon, 19 Feb 2024 08:09:53 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:3c2e:cd45:f50f:f083]) by smtp.gmail.com with ESMTPSA id l14-20020a7bc44e000000b00411d1ce4f9dsm11592670wmi.34.2024.02.19.08.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 08:09:52 -0800 (PST) From: Prabhakar <prabhakar.csengg@gmail.com> X-Google-Original-From: Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Fabrizio Castro <fabrizio.castro.jz@renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Date: Mon, 19 Feb 2024 16:09:10 +0000 Message-Id: <20240219160912.1206647-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219160912.1206647-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240219160912.1206647-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791344304795494925 X-GMAIL-MSGID: 1791344304795494925 |
Series |
Add new Renesas RZ/V2H SoC
|
|
Commit Message
Lad, Prabhakar
Feb. 19, 2024, 4:09 p.m. UTC
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add DT binding documentation for System Controller (SYS) found on RZ/V2H{P} ("R9A09G057") SoC's. SYS block contains the SYS_LSI_DEVID register which can be used to retrieve SoC version information. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> --- Note, the reset index in example node will be update once the CPG support is upstreamed. --- .../soc/renesas/renesas,r9a09g057-sys.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
Comments
On 19/02/2024 17:09, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add DT binding documentation for System Controller (SYS) found on > RZ/V2H{P} ("R9A09G057") SoC's. > > SYS block contains the SYS_LSI_DEVID register which can be used to > retrieve SoC version information. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > + > +additionalProperties: false > + > +examples: > + - | > + extal_clk: extal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; Drop the node, not relevant. > + > + sys: system-controller@10430000 { > + compatible = "renesas,r9a09g057-sys"; > + reg = <0x10430000 0x10000>; > + clocks = <&extal_clk>; > + resets = <&cpg 1>; > + }; Best regards, Krzysztof
Hi Krzysztof, Thank you for the review. On Tue, Feb 20, 2024 at 9:51 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 19/02/2024 17:09, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add DT binding documentation for System Controller (SYS) found on > > RZ/V2H{P} ("R9A09G057") SoC's. > > > > SYS block contains the SYS_LSI_DEVID register which can be used to > > retrieve SoC version information. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + extal_clk: extal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + }; > > Drop the node, not relevant. > OK, I'll drop the clock node in the next version. Cheers, Prabhakar
Hi Prabhakar, Thanks for your patch! On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add DT binding documentation for System Controller (SYS) found on > RZ/V2H{P} ("R9A09G057") SoC's. RZ/V2H(P) > > SYS block contains the SYS_LSI_DEVID register which can be used to > retrieve SoC version information. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sysyaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/V2H{P} System Controller (SYS) > + > +maintainers: > + - Geert Uytterhoeven <geert+renesas@glider.be> > + > +description: > + The RZ/V2H{P} SYS (System Controller) controls the overall RZ/V2H(P) > + configuration of the LSI and supports the following functions, > + - Trust zone control > + - Extend access by specific masters to address beyond 4GB space > + - GBETH configuration > + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU > + - LSI version > + - WDT stop control > + - General registers > + > +properties: > + compatible: > + const: renesas,r9a09g057-sys > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Clock from external oscillator Isn't this SYS_0_PCLK inside the CPG? > + > + resets: > + items: > + - description: SYS_0_PRESETN reset signal > + > +required: > + - compatible > + - reg > + - clocks > + - resets > + > +additionalProperties: false > + > +examples: > + - | > + extal_clk: extal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; > + > + sys: system-controller@10430000 { > + compatible = "renesas,r9a09g057-sys"; > + reg = <0x10430000 0x10000>; > + clocks = <&extal_clk>; clocks = <&cpg 1>; (I guess it will be 1 ;-) > + resets = <&cpg 1>; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > Thanks for your patch! > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmailcom> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add DT binding documentation for System Controller (SYS) found on > > RZ/V2H{P} ("R9A09G057") SoC's. > > RZ/V2H(P) > > > > > SYS block contains the SYS_LSI_DEVID register which can be used to > > retrieve SoC version information. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml > > @@ -0,0 +1,59 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/V2H{P} System Controller (SYS) > > + > > +maintainers: > > + - Geert Uytterhoeven <geert+renesas@glider.be> > > + > > +description: > > + The RZ/V2H{P} SYS (System Controller) controls the overall > > RZ/V2H(P) > OK. > > + configuration of the LSI and supports the following functions, > > + - Trust zone control > > + - Extend access by specific masters to address beyond 4GB space > > + - GBETH configuration > > + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU > > + - LSI version > > + - WDT stop control > > + - General registers > > + > > +properties: > > + compatible: > > + const: renesas,r9a09g057-sys > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Clock from external oscillator > > Isn't this SYS_0_PCLK inside the CPG? > As per the block diagram (figure 4.4-3), if we follow the clock source for SYS it traces back to 24MHz Oscillator. Let me know how you want me to describe this please. > > + > > + resets: > > + items: > > + - description: SYS_0_PRESETN reset signal > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - resets > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + extal_clk: extal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + }; > > + > > + sys: system-controller@10430000 { > > + compatible = "renesas,r9a09g057-sys"; > > + reg = <0x10430000 0x10000>; > > + clocks = <&extal_clk>; > > clocks = <&cpg 1>; > > (I guess it will be 1 ;-) > Yep indeed ;) Cheers, Prabhakar > > + resets = <&cpg 1>; > > + }; > > Gr{oetje,eeting}s, > > Geert > > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Prabhakar, On Mon, Feb 26, 2024 at 3:01 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml > > > + clocks: > > > + items: > > > + - description: Clock from external oscillator > > > > Isn't this SYS_0_PCLK inside the CPG? > > > As per the block diagram (figure 4.4-3), if we follow the clock source > for SYS it traces back to 24MHz Oscillator. Let me know how you want > me to describe this please. Yes, that is the diagram I was looking at. MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK. MAIN OSC 24 MHz is a clock input to the CPG. MAINCLK is a CPG internal core clock. SYS_0_PCLK is a CPG clock output, serving as the SYS module clock. I think the standard "maxItems: 1" would be fine, and no description is needed. > > > + > > > + resets: > > > + items: > > > + - description: SYS_0_PRESETN reset signal Same here. Gr{oetje,eeting}s, Geert
Hi Geert, On Mon, Feb 26, 2024 at 3:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Feb 26, 2024 at 3:01 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml > > > > + clocks: > > > > + items: > > > > + - description: Clock from external oscillator > > > > > > Isn't this SYS_0_PCLK inside the CPG? > > > > > As per the block diagram (figure 4.4-3), if we follow the clock source > > for SYS it traces back to 24MHz Oscillator. Let me know how you want > > me to describe this please. > > Yes, that is the diagram I was looking at. > MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK. > > MAIN OSC 24 MHz is a clock input to the CPG. > MAINCLK is a CPG internal core clock. > SYS_0_PCLK is a CPG clock output, serving as the SYS module clock. > Agreed. > I think the standard "maxItems: 1" would be fine, and no description > is needed. > OK, makes sense. > > > > + > > > > + resets: > > > > + items: > > > > + - description: SYS_0_PRESETN reset signal > > Same here. > Ok. Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml new file mode 100644 index 000000000000..ba30d7734ee8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H{P} System Controller (SYS) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The RZ/V2H{P} SYS (System Controller) controls the overall + configuration of the LSI and supports the following functions, + - Trust zone control + - Extend access by specific masters to address beyond 4GB space + - GBETH configuration + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU + - LSI version + - WDT stop control + - General registers + +properties: + compatible: + const: renesas,r9a09g057-sys + + reg: + maxItems: 1 + + clocks: + items: + - description: Clock from external oscillator + + resets: + items: + - description: SYS_0_PRESETN reset signal + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + sys: system-controller@10430000 { + compatible = "renesas,r9a09g057-sys"; + reg = <0x10430000 0x10000>; + clocks = <&extal_clk>; + resets = <&cpg 1>; + };