Message ID | 20240204074527.47110-4-yangyicong@huawei.com |
---|---|
State | New |
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Commit Message
Yicong Yang
Feb. 4, 2024, 7:45 a.m. UTC
From: Yicong Yang <yangyicong@hisilicon.com> A typical PCIe transaction is consisted of various TLP packets in both direction. For counting bandwidth only memory read events are exported currently. Add memory write and completion counting events of both direction to complementation. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> --- drivers/perf/hisilicon/hisi_pcie_pmu.c | 8 ++++++++ 1 file changed, 8 insertions(+)
Comments
On Sun, 4 Feb 2024 15:45:23 +0800 Yicong Yang <yangyicong@huawei.com> wrote: > From: Yicong Yang <yangyicong@hisilicon.com> > > A typical PCIe transaction is consisted of various TLP packets in both > direction. For counting bandwidth only memory read events are exported > currently. Add memory write and completion counting events of both > direction to complementation. complementation? > > Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/perf/hisilicon/hisi_pcie_pmu.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c > index 9623bed93876..83be3390686c 100644 > --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c > +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c > @@ -726,10 +726,18 @@ static struct attribute *hisi_pcie_pmu_events_attr[] = { > HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210), > HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011), > HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011), > + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_flux, 0x0104), > + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_time, 0x10104), > HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x0804), > HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x10804), > + HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_flux, 0x2004), > + HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_time, 0x12004), > + HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_flux, 0x0105), > + HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_time, 0x10105), > HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x0405), > HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x10405), > + HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_flux, 0x1005), > + HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_time, 0x11005), > NULL > }; >
On 2024/2/8 20:20, Jonathan Cameron wrote: > On Sun, 4 Feb 2024 15:45:23 +0800 > Yicong Yang <yangyicong@huawei.com> wrote: > >> From: Yicong Yang <yangyicong@hisilicon.com> >> >> A typical PCIe transaction is consisted of various TLP packets in both >> direction. For counting bandwidth only memory read events are exported >> currently. Add memory write and completion counting events of both >> direction to complementation. > > complementation? > sorry for the typo. will fix. >> >> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Thanks. > >> --- >> drivers/perf/hisilicon/hisi_pcie_pmu.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c >> index 9623bed93876..83be3390686c 100644 >> --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c >> +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c >> @@ -726,10 +726,18 @@ static struct attribute *hisi_pcie_pmu_events_attr[] = { >> HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210), >> HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011), >> HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011), >> + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_flux, 0x0104), >> + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_time, 0x10104), >> HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x0804), >> HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x10804), >> + HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_flux, 0x2004), >> + HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_time, 0x12004), >> + HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_flux, 0x0105), >> + HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_time, 0x10105), >> HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x0405), >> HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x10405), >> + HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_flux, 0x1005), >> + HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_time, 0x11005), >> NULL >> }; >> > > . >
diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c index 9623bed93876..83be3390686c 100644 --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -726,10 +726,18 @@ static struct attribute *hisi_pcie_pmu_events_attr[] = { HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011), + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_flux, 0x0104), + HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_time, 0x10104), HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x0804), HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x10804), + HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_flux, 0x2004), + HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_time, 0x12004), + HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_flux, 0x0105), + HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_time, 0x10105), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x0405), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x10405), + HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_flux, 0x1005), + HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_time, 0x11005), NULL };