Message ID | 20240219140202.85680-2-christophe.kerello@foss.st.com |
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State | New |
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Mon, 19 Feb 2024 15:03:55 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7AD1A2690DD; Mon, 19 Feb 2024 15:03:29 +0100 (CET) Received: from localhost (10.201.21.177) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 19 Feb 2024 15:03:29 +0100 From: Christophe Kerello <christophe.kerello@foss.st.com> To: <krzysztof.kozlowski@linaro.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <linux-kernel@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <devicetree@vger.kernel.org>, Christophe Kerello <christophe.kerello@foss.st.com> Subject: [PATCH v2 1/5] dt-bindings: memory-controller: st,stm32: add MP25 support Date: Mon, 19 Feb 2024 15:01:58 +0100 Message-ID: <20240219140202.85680-2-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240219140202.85680-1-christophe.kerello@foss.st.com> References: <20240219140202.85680-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-19_10,2024-02-19_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791336355672563593 X-GMAIL-MSGID: 1791336355672563593 |
Series |
memory: stm32-fmc2-ebi: Add MP25 FMC2 support
|
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Commit Message
Christophe Kerello
Feb. 19, 2024, 2:01 p.m. UTC
Add a new compatible string to support MP25 SoC.
On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM
controller signal) have been integrated together in the SoC. That means
that the NAND controller and the PSRAM controller (if the signal is
used) can not be used at the same time. On MP25 SoC, the 2 signals can
be used outside the SoC, so there is no more restrictions.
MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds
revision 2.0 of the FMC2 IP.
MP25 SoC is also using PSCI OS-initiated mode, so allow a single
'power-domains' entry for STM32 FMC2. As MP1 will move on PSCI
OS-initiated mode, add this property as optional for all FMC2 variants.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
---
Changes in v2:
- V1 patch 1 and 2 have been squashed and commit message has been updated.
.../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
Comments
On 19/02/2024 15:01, Christophe Kerello wrote: > Add a new compatible string to support MP25 SoC. > > On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM > controller signal) have been integrated together in the SoC. That means > that the NAND controller and the PSRAM controller (if the signal is > used) can not be used at the same time. On MP25 SoC, the 2 signals can > be used outside the SoC, so there is no more restrictions. > > MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds > revision 2.0 of the FMC2 IP. > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 20/02/2024 10:56, Krzysztof Kozlowski wrote: > On 19/02/2024 15:01, Christophe Kerello wrote: >> Add a new compatible string to support MP25 SoC. >> >> On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM >> controller signal) have been integrated together in the SoC. That means >> that the NAND controller and the PSRAM controller (if the signal is >> used) can not be used at the same time. On MP25 SoC, the 2 signals can >> be used outside the SoC, so there is no more restrictions. >> >> MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds >> revision 2.0 of the FMC2 IP. >> > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Heh, that's actually a patch for me. Un-acked. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37c9..84ac6f50a6fc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -23,7 +23,9 @@ maintainers: properties: compatible: - const: st,stm32mp1-fmc2-ebi + enum: + - st,stm32mp1-fmc2-ebi + - st,stm32mp25-fmc2-ebi reg: maxItems: 1 @@ -34,6 +36,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + "#address-cells": const: 2