Message ID | 20240218174138.1942418-2-martin.blumenstingl@googlemail.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-70461-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp882780dyc; Sun, 18 Feb 2024 09:42:32 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCX5XaJvfZMouK1zqhPlQGUDTV8erFv/Iw3/zL3hYsd08dI5mOpYYlfmNly9s12gj8EqPVsP7w50N5C+m2n6kbOBneOqyw== X-Google-Smtp-Source: AGHT+IEgsiw36KR/PRNadl4acR/kM1W+5t2tlXX21cw5zi68vUOOBIyXUgM2j+CGPsejUJ8EXFaT X-Received: by 2002:a05:6402:345c:b0:564:695e:d70a with SMTP id l28-20020a056402345c00b00564695ed70amr746708edc.41.1708278151941; Sun, 18 Feb 2024 09:42:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708278151; cv=pass; d=google.com; s=arc-20160816; b=i9IvH6EdZLuIG3Tzr9UuTC5j31kfidea9SngRo9Ja0EuGC0MFEwytxLBkyyFWoGkrn hi4hQPX4kUg/GOmU+FM3KEspaQAXwFaVI6CDKbdhZnDRJHuWp4fHVBVpIUbMWpJ99Uft +NEf1oWyHDojG+WZwSyGn/LFoMrEQO4Pr55TiS2PFAoTPlh5x8A3MFrdDs8P9mfYWaC3 opXjmsRMMDRFrQJYRkIQpwV+y36C3dVuzoFb3JbvucLiZajZxpN0jewf/4NfSqMFazzV G7CfWtsiv/iqiyIOR2l8LMenJi7dIjzPdQ2msz9CNPK09mDmCbaVAc54q99vER1N35IS hnQA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ZzWEspu2HplkFu6tE3sVyn+412Gf0v6f/fBl/plDgWc=; fh=WvygN0BxWEf3Ugh+bJepkojgWPAC0oQUD/U+1DFtPlA=; b=ZllwVM7BhLtwBbJxmTyqdZgphtIysgQ2tVX70XjZyLmk7hdhrIMf2Hjkbnx1REGT0A SO8cFfPQv/W7ceyr6IJ31fx+Knun+uDu376VLbrjnf9Sn++g7HNR05XASBuHq/nVkn+a rMu93fK6TQpsVL6w5aQ9WoE5DhzLARBw/Tp6qjUdIJFEyhvdBKAq2Vkby3KTd2q7ntS+ e0wS77F0+nRIvgYnk5Qz8zvffYYpUMmwmQRGtjAPaCWTDl6rnwYv3u5GaDuo5NhTEx+w WNf/DbcV/OC8b8403w4jnwrls2EWkJS+ONOc9soz+kCuHd1d1bu78JG3Rfca4u7YHJ1P r6IA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@googlemail.com header.s=20230601 header.b=EaoRL1ue; arc=pass (i=1 spf=pass spfdomain=googlemail.com dkim=pass dkdomain=googlemail.com dmarc=pass fromdomain=googlemail.com); spf=pass (google.com: domain of linux-kernel+bounces-70461-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-70461-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id w17-20020aa7cb51000000b00561cb3c8c20si1779670edt.246.2024.02.18.09.42.31 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Feb 2024 09:42:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-70461-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20230601 header.b=EaoRL1ue; arc=pass (i=1 spf=pass spfdomain=googlemail.com dkim=pass dkdomain=googlemail.com dmarc=pass fromdomain=googlemail.com); spf=pass (google.com: domain of linux-kernel+bounces-70461-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-70461-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 8BCD91F21268 for <ouuuleilei@gmail.com>; Sun, 18 Feb 2024 17:42:31 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 835466F506; Sun, 18 Feb 2024 17:42:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="EaoRL1ue" Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 408A325777 for <linux-kernel@vger.kernel.org>; Sun, 18 Feb 2024 17:41:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708278119; cv=none; b=VebhZNCQlGPvzKf8Dij0ZE1CDAbEFM/w0C/SX5UE7FZrrJWzr20R9umyE9S/VSCeQQ5p2rjG0f8fSfxYm9KiT/6r8DeUtrsQYPMc4L/dhPTiaqr3G5yLnRxFY66szXVapu6GizGIud858GgyLQOJM+M1rSPn0WsJqILnS6yW3AU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708278119; c=relaxed/simple; bh=9JKkB9Yj8dy244I0oL0qNyEe77jaJB0G5W0EqyXroeE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lIDVBbgiu+wI4dQFuCslK4jdvXONvZqoqJU/a4pII5bzUD9JchNjfJ2n6g6QOfMsfhtPm0yJ3MVToVGe15HLtSg/fbtRuf0OLtjYG1UeM6guxS+w86+pgbTLK50UllAHACFKS5ZjGngUozoPXE9z7q51SBP+3b10H+qxmhmQTgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=googlemail.com; spf=pass smtp.mailfrom=googlemail.com; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b=EaoRL1ue; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=googlemail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=googlemail.com Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-563fe793e1cso2478579a12.3 for <linux-kernel@vger.kernel.org>; Sun, 18 Feb 2024 09:41:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20230601; t=1708278116; x=1708882916; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZzWEspu2HplkFu6tE3sVyn+412Gf0v6f/fBl/plDgWc=; b=EaoRL1ueOrttnwQvGzBfSw7OyJFyENXlSGE8TR8BVWv4d0Jdh9AJfuoKyuXVQfQWuo 2aqA8nkj0oFm1TcIVZeM45H4zp5PXGrO7zWfeqU57Dhlrd8E4lafJG3zqZW5cuaD7srD gZoPI/fMGkngK5otOPH/rz0qlKtw3/oeTGMq5E29eIX2S0Ws3xnzkw0fgA7babW9tkv5 VDhp9zt1Cb9z/pAeuQSmrlQmNXxVDLAoECae31GsBxUBsOODKH+j6Ag8fuYVtOzb8vgB PVSd0PEYQGXPPmVsJv3zq9HpalHeL/dfYsbBSfIARapXP6+9ubG63Ec8F1EdPQdfBvaH WzgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708278116; x=1708882916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZzWEspu2HplkFu6tE3sVyn+412Gf0v6f/fBl/plDgWc=; b=gXP8bgNFhr1oPaLW+IBBkYiZGzzf90DsiYCO/OECJaiI8DJYLBrNuxAsTBOOk+kKP6 oWQHfUz4/dv6Hy03MCcI8vXg0iAtCKt6mesqwXQ2euYhbcWz4bRdGbE2OfJ77Zv24xFI Av9XUoPIzqwFph7yOrAIXVrzLL6Wb939WqFxhwMcdiHzYNr2gMRlJUtVLtgh/ipLS36+ w3BkYWQuWbQbcfi8RX2NlvuygT75qwCck9ExxNndt43OgVFZDzLkAOvp950mZXi0YxfM SeHoJZIYjEWHGFcz76JShweie8chqCqpsE6kWtpin35VywUKZ51eNCJOZDifJt46hzKp SDjw== X-Gm-Message-State: AOJu0Yy4G4gk0AqC7spIjaQ+O/u3ON1DPa6C2IYyd9Jde/I4kx6cjBUK 2uRZcl0P2EN+hS1+b9xRLwD0KE9jGPQkUJ/bLg4wtoPHeRHlgTJzbEn77RfX X-Received: by 2002:a17:906:7196:b0:a3d:1899:ec3 with SMTP id h22-20020a170906719600b00a3d18990ec3mr7343762ejk.35.1708278116629; Sun, 18 Feb 2024 09:41:56 -0800 (PST) Received: from localhost.localdomain (dynamic-2a01-0c22-7b37-4900-0000-0000-0000-0e63.c22.pool.telefonica.de. [2a01:c22:7b37:4900::e63]) by smtp.googlemail.com with ESMTPSA id r16-20020a1709067fd000b00a3e88f99cf1sm412710ejs.149.2024.02.18.09.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Feb 2024 09:41:56 -0800 (PST) From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andrea.merello@gmail.com, patrice.chotard@foss.st.com, linux-amlogic@lists.infradead.org, Martin Blumenstingl <martin.blumenstingl@googlemail.com> Subject: [PATCH v1 1/2] clocksource/drivers/arm_global_timer: Fix maximum prescaler value Date: Sun, 18 Feb 2024 18:41:37 +0100 Message-ID: <20240218174138.1942418-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240218174138.1942418-1-martin.blumenstingl@googlemail.com> References: <20240218174138.1942418-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791259471636476841 X-GMAIL-MSGID: 1791259471636476841 |
Series |
clocksource/drivers/arm_global_timer: Two small fixes
|
|
Commit Message
Martin Blumenstingl
Feb. 18, 2024, 5:41 p.m. UTC
The prescaler in the "Global Timer Control Register bit assignments" is
documented to use bits [15:8], which means that the maximum prescaler
register value is 0xff.
Fixes: 171b45a4a70e ("clocksource/drivers/arm_global_timer: Implement rate compensation whenever source clock changes")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clocksource/arm_global_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On 18/02/2024 18:41, Martin Blumenstingl wrote: > The prescaler in the "Global Timer Control Register bit assignments" is > documented to use bits [15:8], which means that the maximum prescaler > register value is 0xff. > > Fixes: 171b45a4a70e ("clocksource/drivers/arm_global_timer: Implement rate compensation whenever source clock changes") > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > drivers/clocksource/arm_global_timer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c > index 44a61dc6f932..e1c773bb5535 100644 > --- a/drivers/clocksource/arm_global_timer.c > +++ b/drivers/clocksource/arm_global_timer.c > @@ -32,7 +32,7 @@ > #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ > #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ > #define GT_CONTROL_PRESCALER_SHIFT 8 > -#define GT_CONTROL_PRESCALER_MAX 0xF > +#define GT_CONTROL_PRESCALER_MAX 0xFF > #define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \ > GT_CONTROL_PRESCALER_SHIFT Good catch! IMO the initial confusion is coming from the shift and the mask size. But should GT_CONTROL_PRESCALER_MAX be 256 ? so (0xFF + 1) The following may be less confusing: #define GT_CONTROL_PRESCALER_SHIFT 8 #define GT_CONTROL_PRESCALER_MASK GENMASK(15,8) #define GT_CONTROL_PRESCALER_MAX (GT_CONTROL_PRESCALER_MASK >> \ GT_CONTROL_PRESCALER_SHIFT) + 1
Hi Daniel, On Sun, Feb 18, 2024 at 11:59 PM Daniel Lezcano <daniel.lezcano@linaro.org> wrote: [...] > > #define GT_CONTROL_PRESCALER_SHIFT 8 > > -#define GT_CONTROL_PRESCALER_MAX 0xF > > +#define GT_CONTROL_PRESCALER_MAX 0xFF > > #define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \ > > GT_CONTROL_PRESCALER_SHIFT > > Good catch! > > IMO the initial confusion is coming from the shift and the mask size. > > But should GT_CONTROL_PRESCALER_MAX be 256 ? so (0xFF + 1) It depends on what we consider "max" to be: - the register value - the actual number that's used in the calculation formula If we ignore the usage of GT_CONTROL_PRESCALER_MAX within GT_CONTROL_PRESCALER_MASK then there's only one occurrence left, which decrements the calculated value right before comparing it against GT_CONTROL_PRESCALER_MAX. This means: the remaining driver currently considers GT_CONTROL_PRESCALER_MAX to be the maximum value that can be written to the register, having converted the value from the calculation formula to register value beforehand. > The following may be less confusing: > > #define GT_CONTROL_PRESCALER_SHIFT 8 > #define GT_CONTROL_PRESCALER_MASK GENMASK(15,8) > #define GT_CONTROL_PRESCALER_MAX (GT_CONTROL_PRESCALER_MASK >> \ > GT_CONTROL_PRESCALER_SHIFT) + 1 If you're interested then I'll work on a follow-up patch to clean up the prescaler macros (using FIELD_PREP, FIELD_GET and GENMASK would simplify things IMO). I think that this patch is still good as-is since it's small and can be backported easily (if someone wants to do that). Best regards, Martin
On 19/02/2024 00:18, Martin Blumenstingl wrote: > Hi Daniel, > > On Sun, Feb 18, 2024 at 11:59 PM Daniel Lezcano > <daniel.lezcano@linaro.org> wrote: > [...] >>> #define GT_CONTROL_PRESCALER_SHIFT 8 >>> -#define GT_CONTROL_PRESCALER_MAX 0xF >>> +#define GT_CONTROL_PRESCALER_MAX 0xFF >>> #define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \ >>> GT_CONTROL_PRESCALER_SHIFT >> >> Good catch! >> >> IMO the initial confusion is coming from the shift and the mask size. >> >> But should GT_CONTROL_PRESCALER_MAX be 256 ? so (0xFF + 1) > It depends on what we consider "max" to be: > - the register value > - the actual number that's used in the calculation formula > > If we ignore the usage of GT_CONTROL_PRESCALER_MAX within > GT_CONTROL_PRESCALER_MASK then there's only one occurrence left, which > decrements the calculated value right before comparing it against > GT_CONTROL_PRESCALER_MAX. > This means: the remaining driver currently considers > GT_CONTROL_PRESCALER_MAX to be the maximum value that can be written > to the register, having converted the value from the calculation > formula to register value beforehand. > >> The following may be less confusing: >> >> #define GT_CONTROL_PRESCALER_SHIFT 8 >> #define GT_CONTROL_PRESCALER_MASK GENMASK(15,8) >> #define GT_CONTROL_PRESCALER_MAX (GT_CONTROL_PRESCALER_MASK >> \ >> GT_CONTROL_PRESCALER_SHIFT) + 1 > If you're interested then I'll work on a follow-up patch to clean up > the prescaler macros (using FIELD_PREP, FIELD_GET and GENMASK would > simplify things IMO). Yes, cleanups are welcome > I think that this patch is still good as-is since it's small and can > be backported easily (if someone wants to do that). Ok, I'm fine with that
diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c index 44a61dc6f932..e1c773bb5535 100644 --- a/drivers/clocksource/arm_global_timer.c +++ b/drivers/clocksource/arm_global_timer.c @@ -32,7 +32,7 @@ #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ #define GT_CONTROL_PRESCALER_SHIFT 8 -#define GT_CONTROL_PRESCALER_MAX 0xF +#define GT_CONTROL_PRESCALER_MAX 0xFF #define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \ GT_CONTROL_PRESCALER_SHIFT)