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[v5,1/4] riscv/barrier: Define __{mb,rmb,wmb}

Message ID 20240213223909.2596587-1-ericchancf@google.com
State New
Headers
Series riscv/barrier: tidying up barrier-related macro |

Commit Message

Eric Chan Feb. 13, 2024, 10:39 p.m. UTC 
  Introduce __{mb,rmb,wmb}, and rely on the generic definitions for
{mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more
consistent with generic instrumentation.

Signed-off-by: Eric Chan <ericchancf@google.com>
---
 arch/riscv/include/asm/barrier.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Andrea Parri Feb. 16, 2024, 8:30 p.m. UTC | #1 
On Tue, Feb 13, 2024 at 10:39:09PM +0000, Eric Chan wrote:
> Introduce __{mb,rmb,wmb}, and rely on the generic definitions for
> {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more

                                        supported, the code/definitions


> -#define mb()		RISCV_FENCE(iorw,iorw)
> -#define rmb()		RISCV_FENCE(ir,ir)
> -#define wmb()		RISCV_FENCE(ow,ow)
> +#define __mb()		RISCV_FENCE(iorw,iorw)
> +#define __rmb()		RISCV_FENCE(ir,ir)
> +#define __wmb()		RISCV_FENCE(ow,ow)

It seems you forgot to apply Emil's suggestion from v3; please do in v6.
(No need to do something immediately, still reviewing this version.  ;))

  Andrea
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
index 110752594228..4c49a8ff2c68 100644
--- a/arch/riscv/include/asm/barrier.h
+++ b/arch/riscv/include/asm/barrier.h
@@ -20,9 +20,9 @@ 
 	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
 
 /* These barriers need to enforce ordering on both devices or memory. */
-#define mb()		RISCV_FENCE(iorw,iorw)
-#define rmb()		RISCV_FENCE(ir,ir)
-#define wmb()		RISCV_FENCE(ow,ow)
+#define __mb()		RISCV_FENCE(iorw,iorw)
+#define __rmb()		RISCV_FENCE(ir,ir)
+#define __wmb()		RISCV_FENCE(ow,ow)
 
 /* These barriers do not need to enforce ordering on devices, just memory. */
 #define __smp_mb()	RISCV_FENCE(rw,rw)