diff mbox series

[04/10] arm64: dts: qcom: sc8280xp-crd: limit pcie4 link speed

Message ID 20240212165043.26961-5-johan+linaro@kernel.org
State New
Headers
Series arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe |

Commit Message

Johan Hovold Feb. 12, 2024, 4:50 p.m. UTC 
  Limit the WiFi PCIe link speed to Gen2 speed (500 GB/s), which is the
speed that Windows uses.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 ++
 1 file changed, 2 insertions(+)

Comments

Konrad Dybcio Feb. 15, 2024, 8:47 p.m. UTC | #1 
On 12.02.2024 17:50, Johan Hovold wrote:
> Limit the WiFi PCIe link speed to Gen2 speed (500 GB/s), which is the

MB/s

> speed that Windows uses.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---

Hm.. I'dve assumed it ships with a WLAN card that supports moving
more bandwidth.. Is it always at gen2?

Konrad
Johan Hovold Feb. 16, 2024, 7:12 a.m. UTC | #2 
On Thu, Feb 15, 2024 at 09:47:01PM +0100, Konrad Dybcio wrote:
> On 12.02.2024 17:50, Johan Hovold wrote:
> > Limit the WiFi PCIe link speed to Gen2 speed (500 GB/s), which is the
> 
> MB/s

Indeed, thanks for spotting that.

> > speed that Windows uses.
> > 
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > ---
> 
> Hm.. I'dve assumed it ships with a WLAN card that supports moving
> more bandwidth.. Is it always at gen2?

I don't know how the Windows driver works, but the UEFI firmware has
brought the link up at Gen2 and that's also what Windows reported when I
checked. But I was not actually using the wifi when I did so.

But yes, it seems we may be limiting the theoretical maximum data rate
for the wifi this way.

As this appears to fix wifi startup issue reported by one user, and
allows us to enable ITS and AER reporting, perhaps that's acceptable
until the Linux driver can manage to scale the link speed (or we figure
out a more elaborate way of restarting the link at boot).

The PCIe link errors could also indicate that the wifi can not be run
any faster than this on these machines even if my guess is something is
wrong with ASPM implementation. Hopefully Qualcomm will be able to shed
some light on that.

Johan
Johan Hovold Feb. 16, 2024, 12:04 p.m. UTC | #3 
On Fri, Feb 16, 2024 at 08:12:46AM +0100, Johan Hovold wrote:
> On Thu, Feb 15, 2024 at 09:47:01PM +0100, Konrad Dybcio wrote:
> > On 12.02.2024 17:50, Johan Hovold wrote:
> > > Limit the WiFi PCIe link speed to Gen2 speed (500 GB/s), which is the
> > 
> > MB/s
> 
> Indeed, thanks for spotting that.
> 
> > > speed that Windows uses.

> > Hm.. I'dve assumed it ships with a WLAN card that supports moving
> > more bandwidth.. Is it always at gen2?

> But yes, it seems we may be limiting the theoretical maximum data rate
> for the wifi this way.

It looks like the peak wifi speed for these chips is 3.6 Gbps, and it
may be lower for the X13s (and in practice). So 500 MB/s should be more
than enough.

	https://www.qualcomm.com/products/technology/wi-fi/fastconnect/fastconnect-6900

Johan
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index f34c572253f5..8c1fccf8847a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -563,6 +563,8 @@  &pcie3a_phy {
 };
 
 &pcie4 {
+	max-link-speed = <2>;
+
 	perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;