diff mbox series

aarch64: Use vec_perm_indices::new_shrunk_vector in aarch64_evpc_reencode

Message ID 20240213032129.3744441-1-quic_apinski@quicinc.com
State Accepted
Headers
Series aarch64: Use vec_perm_indices::new_shrunk_vector in aarch64_evpc_reencode |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Andrew Pinski (QUIC) Feb. 13, 2024, 3:21 a.m. UTC 
  While working on PERM related stuff, I can across that aarch64_evpc_reencode
was manually figuring out if we shrink the perm indices instead of
using vec_perm_indices::new_shrunk_vector; shrunk was added after reencode
was added.

Built and tested for aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

	PR target/113822
	* config/aarch64/aarch64.cc (aarch64_evpc_reencode): Use
	vec_perm_indices::new_shrunk_vector instead of manually
	going through the indices.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
---
 gcc/config/aarch64/aarch64.cc | 24 +++++-------------------
 1 file changed, 5 insertions(+), 19 deletions(-)

Comments

Richard Sandiford Feb. 14, 2024, 9:27 p.m. UTC | #1 
Andrew Pinski <quic_apinski@quicinc.com> writes:
> While working on PERM related stuff, I can across that aarch64_evpc_reencode
> was manually figuring out if we shrink the perm indices instead of
> using vec_perm_indices::new_shrunk_vector; shrunk was added after reencode
> was added.
>
> Built and tested for aarch64-linux-gnu with no regressions.
>
> gcc/ChangeLog:
>
> 	PR target/113822
> 	* config/aarch64/aarch64.cc (aarch64_evpc_reencode): Use
> 	vec_perm_indices::new_shrunk_vector instead of manually
> 	going through the indices.

Good spot!  OK for stage 1, thanks.

Richard

>
> Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
> ---
>  gcc/config/aarch64/aarch64.cc | 24 +++++-------------------
>  1 file changed, 5 insertions(+), 19 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index 32eae49d4e9..f4ed8b86532 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -25431,7 +25431,6 @@ static bool
>  aarch64_evpc_reencode (struct expand_vec_perm_d *d)
>  {
>    expand_vec_perm_d newd;
> -  unsigned HOST_WIDE_INT nelt;
>  
>    if (d->vec_flags != VEC_ADVSIMD)
>      return false;
> @@ -25446,24 +25445,10 @@ aarch64_evpc_reencode (struct expand_vec_perm_d *d)
>    if (new_mode == word_mode)
>      return false;
>  
> -  /* to_constant is safe since this routine is specific to Advanced SIMD
> -     vectors.  */
> -  nelt = d->perm.length ().to_constant ();
> -
> -  vec_perm_builder newpermconst;
> -  newpermconst.new_vector (nelt / 2, nelt / 2, 1);
> +  vec_perm_indices newpermindices;
>  
> -  /* Convert the perm constant if we can.  Require even, odd as the pairs.  */
> -  for (unsigned int i = 0; i < nelt; i += 2)
> -    {
> -      poly_int64 elt0 = d->perm[i];
> -      poly_int64 elt1 = d->perm[i + 1];
> -      poly_int64 newelt;
> -      if (!multiple_p (elt0, 2, &newelt) || maybe_ne (elt0 + 1, elt1))
> -	return false;
> -      newpermconst.quick_push (newelt.to_constant ());
> -    }
> -  newpermconst.finalize ();
> +  if (!newpermindices.new_shrunk_vector (d->perm, 2))
> +    return false;
>  
>    newd.vmode = new_mode;
>    newd.vec_flags = VEC_ADVSIMD;
> @@ -25475,7 +25460,8 @@ aarch64_evpc_reencode (struct expand_vec_perm_d *d)
>    newd.testing_p = d->testing_p;
>    newd.one_vector_p = d->one_vector_p;
>  
> -  newd.perm.new_vector (newpermconst, newd.one_vector_p ? 1 : 2, nelt / 2);
> +  newd.perm.new_vector (newpermindices.encoding (), newd.one_vector_p ? 1 : 2,
> +			newpermindices.nelts_per_input ());
>    return aarch64_expand_vec_perm_const_1 (&newd);
>  }
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 32eae49d4e9..f4ed8b86532 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -25431,7 +25431,6 @@  static bool
 aarch64_evpc_reencode (struct expand_vec_perm_d *d)
 {
   expand_vec_perm_d newd;
-  unsigned HOST_WIDE_INT nelt;
 
   if (d->vec_flags != VEC_ADVSIMD)
     return false;
@@ -25446,24 +25445,10 @@  aarch64_evpc_reencode (struct expand_vec_perm_d *d)
   if (new_mode == word_mode)
     return false;
 
-  /* to_constant is safe since this routine is specific to Advanced SIMD
-     vectors.  */
-  nelt = d->perm.length ().to_constant ();
-
-  vec_perm_builder newpermconst;
-  newpermconst.new_vector (nelt / 2, nelt / 2, 1);
+  vec_perm_indices newpermindices;
 
-  /* Convert the perm constant if we can.  Require even, odd as the pairs.  */
-  for (unsigned int i = 0; i < nelt; i += 2)
-    {
-      poly_int64 elt0 = d->perm[i];
-      poly_int64 elt1 = d->perm[i + 1];
-      poly_int64 newelt;
-      if (!multiple_p (elt0, 2, &newelt) || maybe_ne (elt0 + 1, elt1))
-	return false;
-      newpermconst.quick_push (newelt.to_constant ());
-    }
-  newpermconst.finalize ();
+  if (!newpermindices.new_shrunk_vector (d->perm, 2))
+    return false;
 
   newd.vmode = new_mode;
   newd.vec_flags = VEC_ADVSIMD;
@@ -25475,7 +25460,8 @@  aarch64_evpc_reencode (struct expand_vec_perm_d *d)
   newd.testing_p = d->testing_p;
   newd.one_vector_p = d->one_vector_p;
 
-  newd.perm.new_vector (newpermconst, newd.one_vector_p ? 1 : 2, nelt / 2);
+  newd.perm.new_vector (newpermindices.encoding (), newd.one_vector_p ? 1 : 2,
+			newpermindices.nelts_per_input ());
   return aarch64_expand_vec_perm_const_1 (&newd);
 }