Message ID | 1666577099-3859-3-git-send-email-xinlei.lee@mediatek.com |
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State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w8-20020aa79548000000b00557bb4f6977si32291409pfq.106.2022.10.23.19.27.25; Sun, 23 Oct 2022 19:27:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=TsJhPHKC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229832AbiJXCF1 (ORCPT <rfc822;pwkd43@gmail.com> + 99 others); Sun, 23 Oct 2022 22:05:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229943AbiJXCFU (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Sun, 23 Oct 2022 22:05:20 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08A9736DCD for <linux-kernel@vger.kernel.org>; Sun, 23 Oct 2022 19:05:13 -0700 (PDT) X-UUID: dae7622024bd4c3b8a6fbece33fe4bfc-20221024 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3wC0wmH7nkybQhVlHhUVEOcxiDVCzEk8gbZNg1jnZMU=; b=TsJhPHKClgx5k92oNNv/TiE/tSL6xoCp/m+Cju9rqIlStAI1EMO+XgUWnAzn4ZVsTOiuO8K0Uo3KbcW8Iq1ruPrq6FZVBy9YW1O1Gf3xlFhpFBVXX31M2B4I/8lDKkHs+rtES6ILskcUjnn4kWhh61gDYW7F+e/Mq3ND37ohur4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:e1ea6796-1b72-464d-9505-83d3fd74b620,IP:0,U RL:0,TC:0,Content:-25,EDM:25,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.12,REQID:e1ea6796-1b72-464d-9505-83d3fd74b620,IP:0,URL :0,TC:0,Content:-25,EDM:25,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:62cd327,CLOUDID:66af6be4-e572-4957-be22-d8f73f3158f9,B ulkID:2210241005101WZSMWZV,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:5,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: dae7622024bd4c3b8a6fbece33fe4bfc-20221024 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from <xinlei.lee@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 572509980; Mon, 24 Oct 2022 10:05:08 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 24 Oct 2022 10:05:06 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 24 Oct 2022 10:05:05 +0800 From: <xinlei.lee@mediatek.com> To: <matthias.bgg@gmail.com>, <rex-bc.chen@mediatek.com>, <angelogioacchino.delregno@collabora.com>, <jason-jh.lin@mediatek.com>, <nfraprado@collabora.com>, <chunkuang.hu@kernel.org>, <p.zabel@pengutronix.de>, <airlied@linux.ie>, <daniel@ffwll.ch> CC: <dri-devel@lists.freedesktop.org>, <linux-mediatek@lists.infradead.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Xinlei Lee <xinlei.lee@mediatek.com>, Jitao Shi <jitao.shi@mediatek.com> Subject: [PATCH v13,2/3] drm: mediatek: Set dpi format in mmsys Date: Mon, 24 Oct 2022 10:04:58 +0800 Message-ID: <1666577099-3859-3-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1666577099-3859-1-git-send-email-xinlei.lee@mediatek.com> References: <1666577099-3859-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="yes" Content-Transfer-Encoding: 8bit X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747534172538080131?= X-GMAIL-MSGID: =?utf-8?q?1747534172538080131?= |
Series |
Add dpi output format control for MT8186
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Commit Message
Xinlei Lee (李昕磊)
Oct. 24, 2022, 2:04 a.m. UTC
From: Xinlei Lee <xinlei.lee@mediatek.com> Dpi output needs to adjust the output format to dual edge for MT8186. Co-developed-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- drivers/gpu/drm/mediatek/mtk_dpi.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
Comments
On 24/10/2022 04:04, xinlei.lee@mediatek.com wrote: > From: Xinlei Lee <xinlei.lee@mediatek.com> > > Dpi output needs to adjust the output format to dual edge for MT8186. > > Co-developed-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> I realized that I took this patch by error. I'll drop it from my tree now. Regards, Matthias > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 630a4e301ef6..ad87ecddf58d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -15,6 +15,7 @@ > #include <linux/of_graph.h> > #include <linux/pinctrl/consumer.h> > #include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > #include <linux/types.h> > > #include <video/videomode.h> > @@ -30,6 +31,7 @@ > #include "mtk_disp_drv.h" > #include "mtk_dpi_regs.h" > #include "mtk_drm_ddp_comp.h" > +#include "mtk_drm_drv.h" > > enum mtk_dpi_out_bit_num { > MTK_DPI_OUT_BIT_NUM_8BITS, > @@ -67,6 +69,7 @@ struct mtk_dpi { > struct drm_connector *connector; > void __iomem *regs; > struct device *dev; > + struct device *mmsys_dev; > struct clk *engine_clk; > struct clk *pixel_clk; > struct clk *tvd_clk; > @@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit { > * @yuv422_en_bit: Enable bit of yuv422. > * @csc_enable_bit: Enable bit of CSC. > * @pixels_per_iter: Quantity of transferred pixels per iteration. > + * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. > */ > struct mtk_dpi_conf { > unsigned int (*cal_factor)(int clock); > @@ -153,6 +157,7 @@ struct mtk_dpi_conf { > u32 yuv422_en_bit; > u32 csc_enable_bit; > u32 pixels_per_iter; > + bool edge_cfg_in_mmsys; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) > @@ -449,8 +454,12 @@ static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) > mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, > dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? > EDGE_SEL : 0, EDGE_SEL); > + if (dpi->conf->edge_cfg_in_mmsys) > + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_DDR_CON); > } else { > mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0); > + if (dpi->conf->edge_cfg_in_mmsys) > + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_SDR_CON); > } > } > > @@ -778,8 +787,10 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) > { > struct mtk_dpi *dpi = dev_get_drvdata(dev); > struct drm_device *drm_dev = data; > + struct mtk_drm_private *priv = drm_dev->dev_private; > int ret; > > + dpi->mmsys_dev = priv->mmsys_dev; > ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, > DRM_MODE_ENCODER_TMDS); > if (ret) {
Hi Matthias, Thank you for responding. Is there anything we can do about this? Best Regards, Allen On Mon, 2022-11-21 at 19:26 +0100, Matthias Brugger wrote: > > On 24/10/2022 04:04, xinlei.lee@mediatek.com wrote: > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > > > Dpi output needs to adjust the output format to dual edge for > > MT8186. > > > > Co-developed-by: Jitao Shi <jitao.shi@mediatek.com> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > > Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > I realized that I took this patch by error. I'll drop it from my tree > now. > > Regards, > Matthias > > > --- > > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > > b/drivers/gpu/drm/mediatek/mtk_dpi.c > > index 630a4e301ef6..ad87ecddf58d 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > > @@ -15,6 +15,7 @@ > > #include <linux/of_graph.h> > > #include <linux/pinctrl/consumer.h> > > #include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > #include <linux/types.h> > > > > #include <video/videomode.h> > > @@ -30,6 +31,7 @@ > > #include "mtk_disp_drv.h" > > #include "mtk_dpi_regs.h" > > #include "mtk_drm_ddp_comp.h" > > +#include "mtk_drm_drv.h" > > > > enum mtk_dpi_out_bit_num { > > MTK_DPI_OUT_BIT_NUM_8BITS, > > @@ -67,6 +69,7 @@ struct mtk_dpi { > > struct drm_connector *connector; > > void __iomem *regs; > > struct device *dev; > > + struct device *mmsys_dev; > > struct clk *engine_clk; > > struct clk *pixel_clk; > > struct clk *tvd_clk; > > @@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit { > > * @yuv422_en_bit: Enable bit of yuv422. > > * @csc_enable_bit: Enable bit of CSC. > > * @pixels_per_iter: Quantity of transferred pixels per > > iteration. > > + * @edge_cfg_in_mmsys: If the edge configuration for DPI's output > > needs to be set in MMSYS. > > */ > > struct mtk_dpi_conf { > > unsigned int (*cal_factor)(int clock); > > @@ -153,6 +157,7 @@ struct mtk_dpi_conf { > > u32 yuv422_en_bit; > > u32 csc_enable_bit; > > u32 pixels_per_iter; > > + bool edge_cfg_in_mmsys; > > }; > > > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 > > val, u32 mask) > > @@ -449,8 +454,12 @@ static void mtk_dpi_dual_edge(struct mtk_dpi > > *dpi) > > mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, > > dpi->output_fmt == > > MEDIA_BUS_FMT_RGB888_2X12_LE ? > > EDGE_SEL : 0, EDGE_SEL); > > + if (dpi->conf->edge_cfg_in_mmsys) > > + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, > > MTK_DPI_RGB888_DDR_CON); > > } else { > > mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, > > 0); > > + if (dpi->conf->edge_cfg_in_mmsys) > > + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, > > MTK_DPI_RGB888_SDR_CON); > > } > > } > > > > @@ -778,8 +787,10 @@ static int mtk_dpi_bind(struct device *dev, > > struct device *master, void *data) > > { > > struct mtk_dpi *dpi = dev_get_drvdata(dev); > > struct drm_device *drm_dev = data; > > + struct mtk_drm_private *priv = drm_dev->dev_private; > > int ret; > > > > + dpi->mmsys_dev = priv->mmsys_dev; > > ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, > > DRM_MODE_ENCODER_TMDS); > > if (ret) {TThank you for responding.
Hi, Xinlei: <xinlei.lee@mediatek.com> 於 2022年10月24日 週一 上午10:05寫道: > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > Dpi output needs to adjust the output format to dual edge for MT8186. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Co-developed-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 630a4e301ef6..ad87ecddf58d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -15,6 +15,7 @@ > #include <linux/of_graph.h> > #include <linux/pinctrl/consumer.h> > #include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > #include <linux/types.h> > > #include <video/videomode.h> > @@ -30,6 +31,7 @@ > #include "mtk_disp_drv.h" > #include "mtk_dpi_regs.h" > #include "mtk_drm_ddp_comp.h" > +#include "mtk_drm_drv.h" > > enum mtk_dpi_out_bit_num { > MTK_DPI_OUT_BIT_NUM_8BITS, > @@ -67,6 +69,7 @@ struct mtk_dpi { > struct drm_connector *connector; > void __iomem *regs; > struct device *dev; > + struct device *mmsys_dev; > struct clk *engine_clk; > struct clk *pixel_clk; > struct clk *tvd_clk; > @@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit { > * @yuv422_en_bit: Enable bit of yuv422. > * @csc_enable_bit: Enable bit of CSC. > * @pixels_per_iter: Quantity of transferred pixels per iteration. > + * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. > */ > struct mtk_dpi_conf { > unsigned int (*cal_factor)(int clock); > @@ -153,6 +157,7 @@ struct mtk_dpi_conf { > u32 yuv422_en_bit; > u32 csc_enable_bit; > u32 pixels_per_iter; > + bool edge_cfg_in_mmsys; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) > @@ -449,8 +454,12 @@ static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) > mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, > dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? > EDGE_SEL : 0, EDGE_SEL); > + if (dpi->conf->edge_cfg_in_mmsys) > + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_DDR_CON); > } else { > mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0); > + if (dpi->conf->edge_cfg_in_mmsys) > + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_SDR_CON); > } > } > > @@ -778,8 +787,10 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) > { > struct mtk_dpi *dpi = dev_get_drvdata(dev); > struct drm_device *drm_dev = data; > + struct mtk_drm_private *priv = drm_dev->dev_private; > int ret; > > + dpi->mmsys_dev = priv->mmsys_dev; > ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, > DRM_MODE_ENCODER_TMDS); > if (ret) { > -- > 2.18.0 >
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 630a4e301ef6..ad87ecddf58d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -15,6 +15,7 @@ #include <linux/of_graph.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> #include <linux/types.h> #include <video/videomode.h> @@ -30,6 +31,7 @@ #include "mtk_disp_drv.h" #include "mtk_dpi_regs.h" #include "mtk_drm_ddp_comp.h" +#include "mtk_drm_drv.h" enum mtk_dpi_out_bit_num { MTK_DPI_OUT_BIT_NUM_8BITS, @@ -67,6 +69,7 @@ struct mtk_dpi { struct drm_connector *connector; void __iomem *regs; struct device *dev; + struct device *mmsys_dev; struct clk *engine_clk; struct clk *pixel_clk; struct clk *tvd_clk; @@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit { * @yuv422_en_bit: Enable bit of yuv422. * @csc_enable_bit: Enable bit of CSC. * @pixels_per_iter: Quantity of transferred pixels per iteration. + * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -153,6 +157,7 @@ struct mtk_dpi_conf { u32 yuv422_en_bit; u32 csc_enable_bit; u32 pixels_per_iter; + bool edge_cfg_in_mmsys; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -449,8 +454,12 @@ static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? EDGE_SEL : 0, EDGE_SEL); + if (dpi->conf->edge_cfg_in_mmsys) + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_DDR_CON); } else { mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0); + if (dpi->conf->edge_cfg_in_mmsys) + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_SDR_CON); } } @@ -778,8 +787,10 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) { struct mtk_dpi *dpi = dev_get_drvdata(dev); struct drm_device *drm_dev = data; + struct mtk_drm_private *priv = drm_dev->dev_private; int ret; + dpi->mmsys_dev = priv->mmsys_dev; ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, DRM_MODE_ENCODER_TMDS); if (ret) {