[-fixes,v2,2/4] dt-bindings: riscv: Add ratified privileged ISA versions

Message ID 20240213033744.4069020-3-samuel.holland@sifive.com
State New
Headers
Series riscv: cbo.zero fixes |

Commit Message

Samuel Holland Feb. 13, 2024, 3:37 a.m. UTC
  The baseline for the RISC-V privileged ISA is version 1.10. Using
features from newer versions of the privileged ISA requires the
supported version to be reported by platform firmware, either in the ISA
string (where the binding already accepts version numbers) or in the
riscv,isa-extensions property. So far two newer versions are ratified.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

Changes in v2:
 - New patch for v2

 .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
  

Comments

Krzysztof Kozlowski Feb. 13, 2024, 8:50 a.m. UTC | #1
On 13/02/2024 04:37, Samuel Holland wrote:
> The baseline for the RISC-V privileged ISA is version 1.10. Using
> features from newer versions of the privileged ISA requires the
> supported version to be reported by platform firmware, either in the ISA
> string (where the binding already accepts version numbers) or in the
> riscv,isa-extensions property. So far two newer versions are ratified.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---

Please Cc DT list.

Standard disclaimer:

Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline), work on fork of kernel
(don't, instead use mainline) or you ignore some maintainers (really
don't). Just use b4 and everything should be fine, although remember
about `b4 prep --auto-to-cc` if you added new patches to the patchset.

You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling.

Please kindly resend and include all necessary To/Cc entries.

Best regards,
Krzysztof
  
Andrew Jones Feb. 13, 2024, 2:25 p.m. UTC | #2
On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
> The baseline for the RISC-V privileged ISA is version 1.10. Using
> features from newer versions of the privileged ISA requires the
> supported version to be reported by platform firmware, either in the ISA
> string (where the binding already accepts version numbers) or in the
> riscv,isa-extensions property. So far two newer versions are ratified.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
> Changes in v2:
>  - New patch for v2
> 
>  .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 63d81dc895e5..7faf22df01af 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -121,6 +121,16 @@ properties:
>              version of the privileged ISA specification.
>  
>          # multi-letter extensions, sorted alphanumerically
> +        - const: sm1p11
> +          description:
> +            The standard Machine ISA v1.11, as ratified in the 20190608
> +            version of the privileged ISA specification.
> +
> +        - const: sm1p12
> +          description:
> +            The standard Machine ISA v1.12, as ratified in the 20211203
> +            version of the privileged ISA specification.
> +
>          - const: smaia
>            description: |
>              The standard Smaia supervisor-level extension for the advanced
> @@ -134,6 +144,16 @@ properties:
>              added by other RISC-V extensions in H/S/VS/U/VU modes and as
>              ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
>  
> +        - const: ss1p11
> +          description:
> +            The standard Supervisor ISA v1.11, as ratified in the 20190608
> +            version of the privileged ISA specification.
> +
> +        - const: ss1p12
> +          description:
> +            The standard Supervisor ISA v1.12, as ratified in the 20211203
> +            version of the privileged ISA specification.
> +
>          - const: ssaia
>            description: |
>              The standard Ssaia supervisor-level extension for the advanced
> -- 
> 2.43.0
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Note, QEMU doesn't add these extensions to the ISA string yet, but I think
it should start, particularly the profile CPU types which should ensure
all the profile's mandatory extensions are added to the ISA string in
order to avoid any confusion.

Thanks,
drew
  
Conor Dooley Feb. 13, 2024, 5:03 p.m. UTC | #3
On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
> The baseline for the RISC-V privileged ISA is version 1.10. Using
> features from newer versions of the privileged ISA requires the
> supported version to be reported by platform firmware, either in the ISA
> string (where the binding already accepts version numbers) or in the
> riscv,isa-extensions property. So far two newer versions are ratified.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
> Changes in v2:
>  - New patch for v2
> 
>  .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 63d81dc895e5..7faf22df01af 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -121,6 +121,16 @@ properties:
>              version of the privileged ISA specification.
>  
>          # multi-letter extensions, sorted alphanumerically

> +        - const: sm1p11

Why are we beholden to this "1p11" format of RVI's? We have free choice
of characters here, what's stopping us using "machine-v1.11", for
example?

Thanks,
Conor.


> +          description:
> +            The standard Machine ISA v1.11, as ratified in the 20190608
> +            version of the privileged ISA specification.
> +
> +        - const: sm1p12
> +          description:
> +            The standard Machine ISA v1.12, as ratified in the 20211203
> +            version of the privileged ISA specification.
> +
>          - const: smaia
>            description: |
>              The standard Smaia supervisor-level extension for the advanced
> @@ -134,6 +144,16 @@ properties:
>              added by other RISC-V extensions in H/S/VS/U/VU modes and as
>              ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
>  
> +        - const: ss1p11
> +          description:
> +            The standard Supervisor ISA v1.11, as ratified in the 20190608
> +            version of the privileged ISA specification.
> +
> +        - const: ss1p12
> +          description:
> +            The standard Supervisor ISA v1.12, as ratified in the 20211203
> +            version of the privileged ISA specification.
> +
>          - const: ssaia
>            description: |
>              The standard Ssaia supervisor-level extension for the advanced
> -- 
> 2.43.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
  
Conor Dooley Feb. 13, 2024, 5:07 p.m. UTC | #4
On Tue, Feb 13, 2024 at 05:03:46PM +0000, Conor Dooley wrote:
> On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
> > The baseline for the RISC-V privileged ISA is version 1.10. Using
> > features from newer versions of the privileged ISA requires the
> > supported version to be reported by platform firmware, either in the ISA
> > string (where the binding already accepts version numbers) or in the
> > riscv,isa-extensions property. So far two newer versions are ratified.
> > 
> > Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> > ---
> > 
> > Changes in v2:
> >  - New patch for v2
> > 
> >  .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index 63d81dc895e5..7faf22df01af 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -121,6 +121,16 @@ properties:
> >              version of the privileged ISA specification.
> >  
> >          # multi-letter extensions, sorted alphanumerically
> 
> > +        - const: sm1p11
> 
> Why are we beholden to this "1p11" format of RVI's? We have free choice
> of characters here, what's stopping us using "machine-v1.11", for
> example?

We could also choose to communicate this using a specific property, but
I have not really thought that one through yet.
  
Stefan O'Rear Feb. 13, 2024, 5:42 p.m. UTC | #5
On Tue, Feb 13, 2024, at 12:03 PM, Conor Dooley wrote:
> On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
>> The baseline for the RISC-V privileged ISA is version 1.10. Using
>> features from newer versions of the privileged ISA requires the
>> supported version to be reported by platform firmware, either in the ISA
>> string (where the binding already accepts version numbers) or in the
>> riscv,isa-extensions property. So far two newer versions are ratified.
>> 
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>> 
>> Changes in v2:
>>  - New patch for v2
>> 
>>  .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++
>>  1 file changed, 20 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> index 63d81dc895e5..7faf22df01af 100644
>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> @@ -121,6 +121,16 @@ properties:
>>              version of the privileged ISA specification.
>>  
>>          # multi-letter extensions, sorted alphanumerically
>
>> +        - const: sm1p11
>
> Why are we beholden to this "1p11" format of RVI's? We have free choice
> of characters here, what's stopping us using "machine-v1.11", for
> example?
>
> Thanks,
> Conor.

I'd prefer to use names that are at least somewhat recognizable, e.g. in
the profiles spec, rather than making up something from whole cloth.

-s

>
>> +          description:
>> +            The standard Machine ISA v1.11, as ratified in the 20190608
>> +            version of the privileged ISA specification.
>> +
>> +        - const: sm1p12
>> +          description:
>> +            The standard Machine ISA v1.12, as ratified in the 20211203
>> +            version of the privileged ISA specification.
>> +
>>          - const: smaia
>>            description: |
>>              The standard Smaia supervisor-level extension for the advanced
>> @@ -134,6 +144,16 @@ properties:
>>              added by other RISC-V extensions in H/S/VS/U/VU modes and as
>>              ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
>>  
>> +        - const: ss1p11
>> +          description:
>> +            The standard Supervisor ISA v1.11, as ratified in the 20190608
>> +            version of the privileged ISA specification.
>> +
>> +        - const: ss1p12
>> +          description:
>> +            The standard Supervisor ISA v1.12, as ratified in the 20211203
>> +            version of the privileged ISA specification.
>> +
>>          - const: ssaia
>>            description: |
>>              The standard Ssaia supervisor-level extension for the advanced
>> -- 
>> 2.43.0
>> 
>> 
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> Attachments:
> * signature.asc
  
Samuel Holland Feb. 13, 2024, 6 p.m. UTC | #6
On 2024-02-13 11:42 AM, Stefan O'Rear wrote:
> On Tue, Feb 13, 2024, at 12:03 PM, Conor Dooley wrote:
>> On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
>>> The baseline for the RISC-V privileged ISA is version 1.10. Using
>>> features from newer versions of the privileged ISA requires the
>>> supported version to be reported by platform firmware, either in the ISA
>>> string (where the binding already accepts version numbers) or in the
>>> riscv,isa-extensions property. So far two newer versions are ratified.
>>>
>>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>>> ---
>>>
>>> Changes in v2:
>>>  - New patch for v2
>>>
>>>  .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++
>>>  1 file changed, 20 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
>>> index 63d81dc895e5..7faf22df01af 100644
>>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
>>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
>>> @@ -121,6 +121,16 @@ properties:
>>>              version of the privileged ISA specification.
>>>  
>>>          # multi-letter extensions, sorted alphanumerically
>>
>>> +        - const: sm1p11
>>
>> Why are we beholden to this "1p11" format of RVI's? We have free choice
>> of characters here, what's stopping us using "machine-v1.11", for
>> example?
> 
> I'd prefer to use names that are at least somewhat recognizable, e.g. in
> the profiles spec, rather than making up something from whole cloth.

Right, exactly. My two immediate reasons for choosing this are:
1) this is the exact name used in the profiles[1][2], and
2) the same list of extensions is used for the riscv,isa-extensions property and
the ISA string, and this is the expected format for the ISA string.

If we want invent something brand new for the DT binding (which I'm not sure we
do), then I would recommend adding a property like riscv,privileged-isa-version,
because that removes the duplication between the Sm and Ss extensions (since
almost all implementations would have both).

On the other hand, there will likely be other extensions in the future that need
version numbers in riscv,isa-extensions. Adding a special case for the
privileged ISA doesn't help with this, whereas deciding on a syntax for version
numbers in the extension name does.

Regards,
Samuel

[1]:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva20s64-mandatory-extensions
[2]:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22s64-mandatory-extensions
  
Conor Dooley Feb. 15, 2024, 1:14 p.m. UTC | #7
On Tue, Feb 13, 2024 at 03:25:44PM +0100, Andrew Jones wrote:
> On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:

> Note, QEMU doesn't add these extensions to the ISA string yet, but I think
> it should start, particularly the profile CPU types which should ensure
> all the profile's mandatory extensions are added to the ISA string in
> order to avoid any confusion.

Something to note about these "mandatory extensions" that are names for
things we already assumed were present - they're utterly useless and any
DT property should note their absence, not presence, in order to be of any
use. Anything parsing a DT cannot see "svbare" and gain any new
information, since the lack of it could be something that predates the
definition of "svbare" or something without "svbare".

Shit, but that's exactly why I deprecated riscv,isa.

Cheers,
Conor.
  
Stefan O'Rear Feb. 16, 2024, 3:41 p.m. UTC | #8
On Thu, Feb 15, 2024, at 8:14 AM, Conor Dooley wrote:
> On Tue, Feb 13, 2024 at 03:25:44PM +0100, Andrew Jones wrote:
>> On Mon, Feb 12, 2024 at 07:37:33PM -0800, Samuel Holland wrote:
>
>> Note, QEMU doesn't add these extensions to the ISA string yet, but I think
>> it should start, particularly the profile CPU types which should ensure
>> all the profile's mandatory extensions are added to the ISA string in
>> order to avoid any confusion.
>
> Something to note about these "mandatory extensions" that are names for
> things we already assumed were present - they're utterly useless and any
> DT property should note their absence, not presence, in order to be of any
> use. Anything parsing a DT cannot see "svbare" and gain any new
> information, since the lack of it could be something that predates the
> definition of "svbare" or something without "svbare".

This is consistent with the way we handle other extensions that are assumed
at compile time - if you build with RISCV_ISA_C=y, omitting "c" from
riscv,isa-extensions will not cause an error.

It's also the case for any extension whatsoever that if that extension is
not present in the device tree, no information is provided.

It might be useful for diagnostic purposes to have a "binding version"
somewhere to indicate which extensions _would_ be documented; not sure if
there is already a mechanism for this.  For extensions that the kernel has
a hard requirement on like svbare, see above.

> Shit, but that's exactly why I deprecated riscv,isa.

If zicsr and zifencei were broken out from i today, there would not be a
problem, because i as specified by riscv,isa-extensions would refer to a
specific version that included zicsr and zifencei with a new name for the
new, smaller version of i.

It's not working here because privileged architecture versions aren't (yet)
included in riscv,isa-extensions.

-s

> Cheers,
> Conor.
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> Attachments:
> * signature.asc
  

Patch

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 63d81dc895e5..7faf22df01af 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -121,6 +121,16 @@  properties:
             version of the privileged ISA specification.
 
         # multi-letter extensions, sorted alphanumerically
+        - const: sm1p11
+          description:
+            The standard Machine ISA v1.11, as ratified in the 20190608
+            version of the privileged ISA specification.
+
+        - const: sm1p12
+          description:
+            The standard Machine ISA v1.12, as ratified in the 20211203
+            version of the privileged ISA specification.
+
         - const: smaia
           description: |
             The standard Smaia supervisor-level extension for the advanced
@@ -134,6 +144,16 @@  properties:
             added by other RISC-V extensions in H/S/VS/U/VU modes and as
             ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
 
+        - const: ss1p11
+          description:
+            The standard Supervisor ISA v1.11, as ratified in the 20190608
+            version of the privileged ISA specification.
+
+        - const: ss1p12
+          description:
+            The standard Supervisor ISA v1.12, as ratified in the 20211203
+            version of the privileged ISA specification.
+
         - const: ssaia
           description: |
             The standard Ssaia supervisor-level extension for the advanced