Message ID | 20231215220343.22523-1-mario.limonciello@amd.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-1739-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9614747dys; Fri, 15 Dec 2023 14:25:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IFIYcuKEdEcXkTvSJP5YJrofdpzi0Mov9h1nT16Yd9JlHmaMzj3W+o9D7jH0SUpeITTwUrM X-Received: by 2002:a05:6a20:3948:b0:190:13db:f460 with SMTP id r8-20020a056a20394800b0019013dbf460mr7981849pzg.9.1702679146088; Fri, 15 Dec 2023 14:25:46 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1702679146; cv=pass; d=google.com; s=arc-20160816; b=1IUxb0KJEkr98fYWlC0SFJ9POZ70kszDfQyATBR/mPEZIMq7Ouhw1dQOTaBDHJ28aw DE5seYMeSL2GPuCo+vvLD3wk/m2CrUWnVc4Lpj0JsTHBLlOmfa4UOq1OVzph3m1+/Z1S aEmDgHntxcA4CChS8ISmI9zZPPdsXl/ACt+0FjqFg/UvImHIP78iHdADT+JZB67Yk3zj FcIZXDEk330iDTdBQQN9hKmFEPdHOWI2E6r7h1jGV3qAhnWVyYQmtRzA7AetvvFEyT6N Us70FSfrZUfNx77jdFAOYjrVBJ1xC3fSAfnVifvHTMW+bsy86f7NBHkWcdsZpcOs9klp 3tfg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature; bh=F8yQiURzbi+JuTiylQT8sVzM/UD+jOTKzIg7VMaTVto=; fh=tc9SYlXOZhtw7UXgbNRbkae7BVF+Xi03bmiDGmcbsgQ=; b=NxO2RSG9A0+l+ZAYlsveP3VzdgpT76qcgC4aCdcIIw/RLfCIX+MgcvlC/0VJQx3ons Ndzow8VJeWPlY7JLfErnBXnxJEacCTaCLt6UqOUgawLE9NVEeRyAg7n/mNE5aN9mq0tB 4ri5q+AnxleLu70k/fcKCjGepV5YkzgR8hvPoi7/4JkZec4OqMfonEt1hujek1mKKj6N Hx3Sgmun+AYhsRtJxQm09sliEigK/yasmdsV6fVXvEj3wCKmUiIRLY+DypE5iUL71uOI 3MlvXFGhAiArMyELKXvjPVbqlGXfBEa8PfR4wXLFjziWzhZJB0iMbSSwoeOi2ZuZ5X9g cFmA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=IgggiDUE; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel+bounces-1739-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-1739-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id z4-20020a170903018400b001d0c5037ef3si13957008plg.336.2023.12.15.14.25.45 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 14:25:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-1739-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=IgggiDUE; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel+bounces-1739-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-1739-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 74AEBB25057 for <ouuuleilei@gmail.com>; Fri, 15 Dec 2023 22:18:33 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1EE2D18EC0; Fri, 15 Dec 2023 22:18:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="IgggiDUE" X-Original-To: linux-kernel@vger.kernel.org Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2058.outbound.protection.outlook.com [40.107.243.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC9E118EA1; Fri, 15 Dec 2023 22:18:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lFb0o2RWX5sq/uQmq9tI0K9ZfUU/hz5rhwowED3BO1x3iv52Vxz37YwYXVGvB+Gcfz7ThwFXI9YHBAaQWFS6gxW6kY1ydvjK34flgMx+RIiPtLtDV2+aNmIt737EDMAtU/UyENsMB9K8wCcKpF+g2wFq+4zNwnsNRdyIYqC1D3j5gEZNdEIY8LW0ILmIGt4Ygu26FjNPfYqVlorQTSoAAAesd3v6h8ip3/0HLGN4JZ5KXgA4/Z0pN92CnAGdJw3NK09Suv9UuQuhs3zT9BHNvyya0zWfq59KX2bqtjuf3jjjItUn+wuumBdXNORR+2XpoQKRHtnuYHwYs0KUNcuztg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=F8yQiURzbi+JuTiylQT8sVzM/UD+jOTKzIg7VMaTVto=; b=U6WXLtrqP1snoH9vcjC89kO9usB1JQqZcamoltf/m7fixDTL3Ix/QJzSEt1UCZNa34NfR1BaRZO/Zj8xU4eqvq7ua8egwuItXIokFB9CtIf7DhhGayYUl7+r2Vi/fkWtIcTVWEDWGmu4h9kSx/hZcMgYBQ5+h2VghUMuv+AHcMajmgD7VEHK/lAry5wJZLSsMCUSu3aqgRepXWZ68VV5rA3bzHinE6IiF+jSzBT5LsQB2TcCRtWymyfofo7UmP6B2Stt5uusnioCwc8z5xEn0qKJjoIYxi2KJmLRg9xYhFLBaT8EWAzQp/3WwaqIuH0mj9Ffj9urQmYkp75q/3SLpg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=google.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=F8yQiURzbi+JuTiylQT8sVzM/UD+jOTKzIg7VMaTVto=; b=IgggiDUEVdvRBzbJv6jY1ukH56/8FjrchIpNiLxD2goHEXnSEvB5mXswTtvrcCoCCdrd2LzZNyx9ullQcOvdz5yJGm9vUfIPBYs7cT5Wih6Ba9Llfcq6Ug5QP9Zy/s+XKjz3wANOY+z1evD+qU+8nJVv4XQX3p4ZNaPMlNtdpaQ= Received: from MW4PR03CA0279.namprd03.prod.outlook.com (2603:10b6:303:b5::14) by MW4PR12MB7215.namprd12.prod.outlook.com (2603:10b6:303:228::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.33; Fri, 15 Dec 2023 22:18:06 +0000 Received: from CO1PEPF000042A9.namprd03.prod.outlook.com (2603:10b6:303:b5:cafe::43) by MW4PR03CA0279.outlook.office365.com (2603:10b6:303:b5::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.32 via Frontend Transport; Fri, 15 Dec 2023 22:18:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A9.mail.protection.outlook.com (10.167.243.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7113.14 via Frontend Transport; Fri, 15 Dec 2023 22:18:05 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 15 Dec 2023 16:17:52 -0600 From: Mario Limonciello <mario.limonciello@amd.com> To: Bjorn Helgaas <bhelgaas@google.com>, "Rafael J . Wysocki" <rjw@rjwysocki.net> CC: <linux-pci@vger.kernel.org>, <linux-acpi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Mario Limonciello <mario.limonciello@amd.com> Subject: [PATCH v2] x86/pci: Stop requiring ECAM to be declared in E820, ACPI or EFI Date: Fri, 15 Dec 2023 16:03:43 -0600 Message-ID: <20231215220343.22523-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|MW4PR12MB7215:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ca13cbe-4fcf-4a24-48ad-08dbfdbbb631 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2ZW2w8jTSle3yfckqkqBiSR/8N6dexdLn0niCSZBH8QcmH6oywZdlQKfc8isb+kUkrGm0BPu9MQWgOpF94CyU+UYMrptg+7MX3bV76bX+/vryFYX9w3c/GYpoKTnv002GFUoobfrWZUS9aPQwjpia1gcGMhObocJMjY5jfB8WnqCxmDoB3sgsq2i44EwoE+EMQzWzyl51kEbo3cBPTPGTg8qGPSD2f5IXUbRWPZ5g3VVYQYRY3rwcrkLQOcoit5Yzj8EirykexMmGxd31nTtk55gsTpEg2HnGk/89eXJrCZKcZrEJ9X7QTR0aSkRyoi+1302NLtjA09Gcggis21ixGEX0fUleZMXE5WSXZDLb17jh4NBN+twfscQxhgFPnNdYnFOHdamF0/8Yi+TMTAoOGQ6g9nUGKgCNbA+tLEsbnUDAz0Vlz+dD1dRNgl8i6n/q+J2nCtHRZatDJliXl8C+tTKnkaMtXLgPXfLdJfVOC7GskhsikDFO1kyQRFBrpLGt+I6KfThpF11ZFd4Zcp05abw6ujlnUCo3FqZAKoh6ru4QJtfDsofR/f44MRy3QH7aThJT7S/1Of2QIHOAnPOvgOVNYgK+xkyxwwHV/ceToOs85wWN9vJhNlUXm6m4BN9j3vgY4tw7Phvlupls250H/nXKuqYoZGYO34gAsYLbzpLC9z4kSzqnp1a/AjLyzcaIfUHgnsxaTMxhp1GS3WqlZGLZYVUkphoMiEjFyB6MO+Aq2HXGT+OBfQovMN5NFSceYOv/irgMfWDJU0dV7NvOA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(396003)(346002)(376002)(230922051799003)(186009)(451199024)(82310400011)(1800799012)(64100799003)(40470700004)(36840700001)(46966006)(83380400001)(966005)(478600001)(82740400003)(6666004)(7696005)(1076003)(40480700001)(2616005)(426003)(336012)(16526019)(26005)(110136005)(54906003)(316002)(70206006)(70586007)(356005)(81166007)(36860700001)(47076005)(86362001)(8676002)(4326008)(44832011)(40460700003)(8936002)(5660300002)(2906002)(36756003)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2023 22:18:05.8889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ca13cbe-4fcf-4a24-48ad-08dbfdbbb631 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7215 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785388488338604202 X-GMAIL-MSGID: 1785388488338604202 |
Series |
[v2] x86/pci: Stop requiring ECAM to be declared in E820, ACPI or EFI
|
|
Commit Message
Mario Limonciello
Dec. 15, 2023, 10:03 p.m. UTC
commit 7752d5cfe3d1 ("x86: validate against acpi motherboard resources")
introduced checks for ensuring that MCFG table also has memory region
reservations to ensure no conflicts were introduced from a buggy BIOS.
This has proceeded over time to add other types of reservation checks
for ACPI PNP resources and EFI MMIO memory type. The PCI firmware spec
does say that these checks are only required when the operating system
doesn't comprehend the firmware region:
```
If the operating system does not natively comprehend reserving the MMCFG
region, the MMCFG region must be reserved by firmware. The address range
reported in the MCFG table or by _CBA method (see Section 4.1.3) must be
reserved by declaring a motherboard resource. For most systems, the
motherboard resource would appear at the root of the ACPI namespace
(under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources
in this case should not be claimed in the root PCI bus’s _CRS. The
resources can optionally be returned in Int15 E820h or EFIGetMemoryMap
as reserved memory but must always be reported through ACPI as a
motherboard resource.
```
Running this check causes problems with accessing extended PCI
configuration space on OEM laptops that don't specify the region in PNP
resources or in the EFI memory map. That later manifests as problems with
dGPU and accessing resizable BAR. Similar problems don't exist in Windows
11 with exact same laptop/firmware stack.
Due to the stability of the Windows ecosystem that x86 machines participate
it is unlikely that using the region specified in the MCFG table as
a reservation will cause a problem. The possible worst circumstance could
be that a buggy BIOS causes a larger hole in the memory map that is
unusable for devices than intended.
Change the default behavior to keep the region specified in MCFG even if
it's not specified in another source. This is expected to improve
machines that otherwise couldn't access PCI extended configuration space.
In case this change causes problems, add a kernel command line parameter
that can restore the previous behavior.
Link: https://members.pcisig.com/wg/PCI-SIG/document/15350
PCI Firmware Specification 3.3
Section 4.1.2 MCFG Table Description Note 2
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
v1->v2:
* Rebase on pci/next
* Add an escape hatch
* Reword commit message
---
.../admin-guide/kernel-parameters.txt | 6 ++++++
arch/x86/pci/mmconfig-shared.c | 19 +++++++++++++++----
2 files changed, 21 insertions(+), 4 deletions(-)
base-commit: 67e04d921cb6902e8c2abdbf748279d43f25213e
Comments
On 12/15/2023 16:03, Mario Limonciello wrote: > commit 7752d5cfe3d1 ("x86: validate against acpi motherboard resources") > introduced checks for ensuring that MCFG table also has memory region > reservations to ensure no conflicts were introduced from a buggy BIOS. > > This has proceeded over time to add other types of reservation checks > for ACPI PNP resources and EFI MMIO memory type. The PCI firmware spec > does say that these checks are only required when the operating system > doesn't comprehend the firmware region: > > ``` > If the operating system does not natively comprehend reserving the MMCFG > region, the MMCFG region must be reserved by firmware. The address range > reported in the MCFG table or by _CBA method (see Section 4.1.3) must be > reserved by declaring a motherboard resource. For most systems, the > motherboard resource would appear at the root of the ACPI namespace > (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources > in this case should not be claimed in the root PCI bus’s _CRS. The > resources can optionally be returned in Int15 E820h or EFIGetMemoryMap > as reserved memory but must always be reported through ACPI as a > motherboard resource. > ``` > > Running this check causes problems with accessing extended PCI > configuration space on OEM laptops that don't specify the region in PNP > resources or in the EFI memory map. That later manifests as problems with > dGPU and accessing resizable BAR. Similar problems don't exist in Windows > 11 with exact same laptop/firmware stack. > > Due to the stability of the Windows ecosystem that x86 machines participate > it is unlikely that using the region specified in the MCFG table as > a reservation will cause a problem. The possible worst circumstance could > be that a buggy BIOS causes a larger hole in the memory map that is > unusable for devices than intended. > > Change the default behavior to keep the region specified in MCFG even if > it's not specified in another source. This is expected to improve > machines that otherwise couldn't access PCI extended configuration space. > > In case this change causes problems, add a kernel command line parameter > that can restore the previous behavior. > > Link: https://members.pcisig.com/wg/PCI-SIG/document/15350 > PCI Firmware Specification 3.3 > Section 4.1.2 MCFG Table Description Note 2 > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> > --- Bjorn, Any thoughts on this version since our last conversation on V1? Thanks, > v1->v2: > * Rebase on pci/next > * Add an escape hatch > * Reword commit message > --- > .../admin-guide/kernel-parameters.txt | 6 ++++++ > arch/x86/pci/mmconfig-shared.c | 19 +++++++++++++++---- > 2 files changed, 21 insertions(+), 4 deletions(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 65731b060e3f..eacd0c0521c2 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -1473,6 +1473,12 @@ > (in particular on some ATI chipsets). > The kernel tries to set a reasonable default. > > + enforce_ecam_resv [X86] > + Enforce requiring an ECAM reservation specified in > + BIOS for PCI devices. > + This parameter is only valid if CONFIG_PCI_MMCONFIG > + is enabled. > + > enforcing= [SELINUX] Set initial enforcing status. > Format: {"0" | "1"} > See security/selinux/Kconfig help text. > diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c > index 0cc9520666ef..aee117c6bbf9 100644 > --- a/arch/x86/pci/mmconfig-shared.c > +++ b/arch/x86/pci/mmconfig-shared.c > @@ -34,6 +34,15 @@ static DEFINE_MUTEX(pci_mmcfg_lock); > > LIST_HEAD(pci_mmcfg_list); > > +static bool enforce_ecam_resv __read_mostly; > +static int __init parse_ecam_options(char *str) > +{ > + enforce_ecam_resv = true; > + > + return 1; > +} > +__setup("enforce_ecam_resv", parse_ecam_options); > + > static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) > { > if (cfg->res.parent) > @@ -569,10 +578,12 @@ static void __init pci_mmcfg_reject_broken(int early) > > list_for_each_entry(cfg, &pci_mmcfg_list, list) { > if (!pci_mmcfg_reserved(NULL, cfg, early)) { > - pr_info("not using ECAM (%pR not reserved)\n", > - &cfg->res); > - free_all_mmcfg(); > - return; > + pr_info("ECAM %pR not reserved, %s\n", &cfg->res, > + enforce_ecam_resv ? "ignoring" : "using anyway"); > + if (enforce_ecam_resv) { > + free_all_mmcfg(); > + return; > + } > } > } > } > > base-commit: 67e04d921cb6902e8c2abdbf748279d43f25213e
On Wed, Jan 17, 2024 at 11:53:50AM -0600, Mario Limonciello wrote: > On 12/15/2023 16:03, Mario Limonciello wrote: > > commit 7752d5cfe3d1 ("x86: validate against acpi motherboard resources") > > introduced checks for ensuring that MCFG table also has memory region > > reservations to ensure no conflicts were introduced from a buggy BIOS. > > > > This has proceeded over time to add other types of reservation checks > > for ACPI PNP resources and EFI MMIO memory type. The PCI firmware spec > > does say that these checks are only required when the operating system > > doesn't comprehend the firmware region: > > > > ``` > > If the operating system does not natively comprehend reserving the MMCFG > > region, the MMCFG region must be reserved by firmware. The address range > > reported in the MCFG table or by _CBA method (see Section 4.1.3) must be > > reserved by declaring a motherboard resource. For most systems, the > > motherboard resource would appear at the root of the ACPI namespace > > (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources > > in this case should not be claimed in the root PCI bus’s _CRS. The > > resources can optionally be returned in Int15 E820h or EFIGetMemoryMap > > as reserved memory but must always be reported through ACPI as a > > motherboard resource. > > ``` > > > > Running this check causes problems with accessing extended PCI > > configuration space on OEM laptops that don't specify the region in PNP > > resources or in the EFI memory map. That later manifests as problems with > > dGPU and accessing resizable BAR. Similar problems don't exist in Windows > > 11 with exact same laptop/firmware stack. > > > > Due to the stability of the Windows ecosystem that x86 machines participate > > it is unlikely that using the region specified in the MCFG table as > > a reservation will cause a problem. The possible worst circumstance could > > be that a buggy BIOS causes a larger hole in the memory map that is > > unusable for devices than intended. > > > > Change the default behavior to keep the region specified in MCFG even if > > it's not specified in another source. This is expected to improve > > machines that otherwise couldn't access PCI extended configuration space. > > > > In case this change causes problems, add a kernel command line parameter > > that can restore the previous behavior. > > > > Link: https://members.pcisig.com/wg/PCI-SIG/document/15350 > > PCI Firmware Specification 3.3 > > Section 4.1.2 MCFG Table Description Note 2 > > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> > > --- > > Bjorn, > > Any thoughts on this version since our last conversation on V1? Just to let you know that I'm not ignoring this, and I'm trying to formulate a useful response. mmconfig-shared.c has grown into an extremely complicated mess and is a continual source of problems, so I'd really like to untangle it a tiny bit if we can. One thing is that per spec, ACPI motherboard resources are the ONLY way to reserve ECAM space. I'd like to reclaim a little clarity about that and separate out the E820 and EFI stuff as secondary hacks. But there's an insane amount of history that got us here. The problem we have to avoid is assigning a BAR that overlaps ECAM. We assign BARs for lots of reasons. dGPU and resizable BARs are examples but there are others, like hotplug and SR-IOV. The fact that Windows works is a red herring because it allocates BARs differently. It's also little bit of a burr under my saddle to add things for a problem on unspecified machines, where I don't even know whether the machines are already in the field or the firmware could still be fixed. And of course, if there's any way to solve this safely without adding yet another kernel parameter, that would be vastly preferable. Sorry, nothing actionable here but wanted to let you know that it's keeping me awake at night ;) Bjorn > > v1->v2: > > * Rebase on pci/next > > * Add an escape hatch > > * Reword commit message > > --- > > .../admin-guide/kernel-parameters.txt | 6 ++++++ > > arch/x86/pci/mmconfig-shared.c | 19 +++++++++++++++---- > > 2 files changed, 21 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > > index 65731b060e3f..eacd0c0521c2 100644 > > --- a/Documentation/admin-guide/kernel-parameters.txt > > +++ b/Documentation/admin-guide/kernel-parameters.txt > > @@ -1473,6 +1473,12 @@ > > (in particular on some ATI chipsets). > > The kernel tries to set a reasonable default. > > + enforce_ecam_resv [X86] > > + Enforce requiring an ECAM reservation specified in > > + BIOS for PCI devices. > > + This parameter is only valid if CONFIG_PCI_MMCONFIG > > + is enabled. > > + > > enforcing= [SELINUX] Set initial enforcing status. > > Format: {"0" | "1"} > > See security/selinux/Kconfig help text. > > diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c > > index 0cc9520666ef..aee117c6bbf9 100644 > > --- a/arch/x86/pci/mmconfig-shared.c > > +++ b/arch/x86/pci/mmconfig-shared.c > > @@ -34,6 +34,15 @@ static DEFINE_MUTEX(pci_mmcfg_lock); > > LIST_HEAD(pci_mmcfg_list); > > +static bool enforce_ecam_resv __read_mostly; > > +static int __init parse_ecam_options(char *str) > > +{ > > + enforce_ecam_resv = true; > > + > > + return 1; > > +} > > +__setup("enforce_ecam_resv", parse_ecam_options); > > + > > static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) > > { > > if (cfg->res.parent) > > @@ -569,10 +578,12 @@ static void __init pci_mmcfg_reject_broken(int early) > > list_for_each_entry(cfg, &pci_mmcfg_list, list) { > > if (!pci_mmcfg_reserved(NULL, cfg, early)) { > > - pr_info("not using ECAM (%pR not reserved)\n", > > - &cfg->res); > > - free_all_mmcfg(); > > - return; > > + pr_info("ECAM %pR not reserved, %s\n", &cfg->res, > > + enforce_ecam_resv ? "ignoring" : "using anyway"); > > + if (enforce_ecam_resv) { > > + free_all_mmcfg(); > > + return; > > + } > > } > > } > > } > > > > base-commit: 67e04d921cb6902e8c2abdbf748279d43f25213e >
On 1/25/2024 18:35, Bjorn Helgaas wrote: > On Wed, Jan 17, 2024 at 11:53:50AM -0600, Mario Limonciello wrote: >> On 12/15/2023 16:03, Mario Limonciello wrote: >>> commit 7752d5cfe3d1 ("x86: validate against acpi motherboard resources") >>> introduced checks for ensuring that MCFG table also has memory region >>> reservations to ensure no conflicts were introduced from a buggy BIOS. >>> >>> This has proceeded over time to add other types of reservation checks >>> for ACPI PNP resources and EFI MMIO memory type. The PCI firmware spec >>> does say that these checks are only required when the operating system >>> doesn't comprehend the firmware region: >>> >>> ``` >>> If the operating system does not natively comprehend reserving the MMCFG >>> region, the MMCFG region must be reserved by firmware. The address range >>> reported in the MCFG table or by _CBA method (see Section 4.1.3) must be >>> reserved by declaring a motherboard resource. For most systems, the >>> motherboard resource would appear at the root of the ACPI namespace >>> (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources >>> in this case should not be claimed in the root PCI bus’s _CRS. The >>> resources can optionally be returned in Int15 E820h or EFIGetMemoryMap >>> as reserved memory but must always be reported through ACPI as a >>> motherboard resource. >>> ``` >>> >>> Running this check causes problems with accessing extended PCI >>> configuration space on OEM laptops that don't specify the region in PNP >>> resources or in the EFI memory map. That later manifests as problems with >>> dGPU and accessing resizable BAR. Similar problems don't exist in Windows >>> 11 with exact same laptop/firmware stack. >>> >>> Due to the stability of the Windows ecosystem that x86 machines participate >>> it is unlikely that using the region specified in the MCFG table as >>> a reservation will cause a problem. The possible worst circumstance could >>> be that a buggy BIOS causes a larger hole in the memory map that is >>> unusable for devices than intended. >>> >>> Change the default behavior to keep the region specified in MCFG even if >>> it's not specified in another source. This is expected to improve >>> machines that otherwise couldn't access PCI extended configuration space. >>> >>> In case this change causes problems, add a kernel command line parameter >>> that can restore the previous behavior. >>> >>> Link: https://members.pcisig.com/wg/PCI-SIG/document/15350 >>> PCI Firmware Specification 3.3 >>> Section 4.1.2 MCFG Table Description Note 2 >>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> >>> --- >> >> Bjorn, >> >> Any thoughts on this version since our last conversation on V1? > > Just to let you know that I'm not ignoring this, and I'm trying to > formulate a useful response. Thanks, I had been wondering. FYI - we've also added another place to make noise about this ECAM issue in AMDGPU. This warning should go into 6.9: https://lore.kernel.org/amd-gfx/20240110101319.695169-1-Jun.Ma2@amd.com/ It will at least be interesting to see how many people come out of the woodwork to report that new warning. > mmconfig-shared.c has grown into an > extremely complicated mess and is a continual source of problems, so > I'd really like to untangle it a tiny bit if we can. > > One thing is that per spec, ACPI motherboard resources are the ONLY > way to reserve ECAM space. I'd like to reclaim a little clarity about > that and separate out the E820 and EFI stuff as secondary hacks. But > there's an insane amount of history that got us here. I guess you know better than anyone here. But if my idea is actually viable then the E820 and EFI stuff turn into "information only". > > The problem we have to avoid is assigning a BAR that overlaps ECAM. > We assign BARs for lots of reasons. dGPU and resizable BARs are > examples but there are others, like hotplug and SR-IOV. The fact that > Windows works is a red herring because it allocates BARs differently. Have we actually observed a case that assigning the BAR overlaps ECAM region thus far or it's hypothetical? I would think that if the reservation is made by ECAM first, then any conflict for any reason that tries to assign it will just get a smaller BAR, but not necessarily a functional problem. But that's also part of why I was thinking kernel command line for us to have the escape hatch. > > It's also little bit of a burr under my saddle to add things for a > problem on unspecified machines, where I don't even know whether the > machines are already in the field or the firmware could still be > fixed. Of the two machines I know of: * One of them has been fixed by a BIOS change before it's final production stage. * The other is still affected. Here is the info for the still affected one. It's been shipping already. Alienware Alienware m18 R1 AMD/0RU01H, BIOS 1.2.2 04/21/2023 > > And of course, if there's any way to solve this safely without adding > yet another kernel parameter, that would be vastly preferable. The kernel isn't static though; something we could do is keep the parameter around a year or two to get the bug feedback loop of people testing it and then rip it out if nothing comes up. > > Sorry, nothing actionable here but wanted to let you know that it's > keeping me awake at night ;) :) > > Bjorn > >>> v1->v2: >>> * Rebase on pci/next >>> * Add an escape hatch >>> * Reword commit message >>> --- >>> .../admin-guide/kernel-parameters.txt | 6 ++++++ >>> arch/x86/pci/mmconfig-shared.c | 19 +++++++++++++++---- >>> 2 files changed, 21 insertions(+), 4 deletions(-) >>> >>> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt >>> index 65731b060e3f..eacd0c0521c2 100644 >>> --- a/Documentation/admin-guide/kernel-parameters.txt >>> +++ b/Documentation/admin-guide/kernel-parameters.txt >>> @@ -1473,6 +1473,12 @@ >>> (in particular on some ATI chipsets). >>> The kernel tries to set a reasonable default. >>> + enforce_ecam_resv [X86] >>> + Enforce requiring an ECAM reservation specified in >>> + BIOS for PCI devices. >>> + This parameter is only valid if CONFIG_PCI_MMCONFIG >>> + is enabled. >>> + >>> enforcing= [SELINUX] Set initial enforcing status. >>> Format: {"0" | "1"} >>> See security/selinux/Kconfig help text. >>> diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c >>> index 0cc9520666ef..aee117c6bbf9 100644 >>> --- a/arch/x86/pci/mmconfig-shared.c >>> +++ b/arch/x86/pci/mmconfig-shared.c >>> @@ -34,6 +34,15 @@ static DEFINE_MUTEX(pci_mmcfg_lock); >>> LIST_HEAD(pci_mmcfg_list); >>> +static bool enforce_ecam_resv __read_mostly; >>> +static int __init parse_ecam_options(char *str) >>> +{ >>> + enforce_ecam_resv = true; >>> + >>> + return 1; >>> +} >>> +__setup("enforce_ecam_resv", parse_ecam_options); >>> + >>> static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) >>> { >>> if (cfg->res.parent) >>> @@ -569,10 +578,12 @@ static void __init pci_mmcfg_reject_broken(int early) >>> list_for_each_entry(cfg, &pci_mmcfg_list, list) { >>> if (!pci_mmcfg_reserved(NULL, cfg, early)) { >>> - pr_info("not using ECAM (%pR not reserved)\n", >>> - &cfg->res); >>> - free_all_mmcfg(); >>> - return; >>> + pr_info("ECAM %pR not reserved, %s\n", &cfg->res, >>> + enforce_ecam_resv ? "ignoring" : "using anyway"); >>> + if (enforce_ecam_resv) { >>> + free_all_mmcfg(); >>> + return; >>> + } >>> } >>> } >>> } >>> >>> base-commit: 67e04d921cb6902e8c2abdbf748279d43f25213e >>
On Fri, Jan 26, 2024 at 12:32:34PM -0600, Mario Limonciello wrote: > On 1/25/2024 18:35, Bjorn Helgaas wrote: > > On Wed, Jan 17, 2024 at 11:53:50AM -0600, Mario Limonciello wrote: > > > On 12/15/2023 16:03, Mario Limonciello wrote: > > > > commit 7752d5cfe3d1 ("x86: validate against acpi motherboard resources") > > > > introduced checks for ensuring that MCFG table also has memory region > > > > reservations to ensure no conflicts were introduced from a buggy BIOS. > ... > > > Any thoughts on this version since our last conversation on V1? > > > > Just to let you know that I'm not ignoring this, and I'm trying to > > formulate a useful response. > > Thanks, I had been wondering. > > FYI - we've also added another place to make noise about this ECAM > issue in AMDGPU. This warning should go into 6.9: > > https://lore.kernel.org/amd-gfx/20240110101319.695169-1-Jun.Ma2@amd.com/ Looks similar to the PCI core warning here: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/probe.c?id=v6.7#n1134 The comment says it doesn't work for devices on the root bus, though. Maybe it could be made to work there as well? > > mmconfig-shared.c has grown into an > > extremely complicated mess and is a continual source of problems, so > > I'd really like to untangle it a tiny bit if we can. > > > > One thing is that per spec, ACPI motherboard resources are the ONLY > > way to reserve ECAM space. I'd like to reclaim a little clarity about > > that and separate out the E820 and EFI stuff as secondary hacks. But > > there's an insane amount of history that got us here. > > I guess you know better than anyone here. But if my idea is > actually viable then the E820 and EFI stuff turn into "information > only". That would definitely be a good thing. I would like it if that were more obvious from reading the code because I spend waaay too much time staring at that labyrinth. > > The problem we have to avoid is assigning a BAR that overlaps ECAM. > > We assign BARs for lots of reasons. dGPU and resizable BARs are > > examples but there are others, like hotplug and SR-IOV. The fact that > > Windows works is a red herring because it allocates BARs differently. > > Have we actually observed a case that assigning the BAR overlaps > ECAM region thus far or it's hypothetical? Yes, it has happened. There's an example in the commit log here: https://git.kernel.org/linus/070909e56a7d ("x86/pci: Reserve ECAM if BIOS didn't include it in PNP0C02 _CRS") > > And of course, if there's any way to solve this safely without > > adding yet another kernel parameter, that would be vastly > > preferable. > > The kernel isn't static though; something we could do is keep the > parameter around a year or two to get the bug feedback loop of > people testing it and then rip it out if nothing comes up. Yeah. It's pretty hard to remove those options though. For example, "pci=routeirq" was added in the pre-git era and probably isn't necessary, but how do we know nobody uses it? Bjorn
On 1/26/2024 13:29, Bjorn Helgaas wrote: > On Fri, Jan 26, 2024 at 12:32:34PM -0600, Mario Limonciello wrote: >> On 1/25/2024 18:35, Bjorn Helgaas wrote: >>> On Wed, Jan 17, 2024 at 11:53:50AM -0600, Mario Limonciello wrote: >>>> On 12/15/2023 16:03, Mario Limonciello wrote: >>>>> commit 7752d5cfe3d1 ("x86: validate against acpi motherboard resources") >>>>> introduced checks for ensuring that MCFG table also has memory region >>>>> reservations to ensure no conflicts were introduced from a buggy BIOS. >> ... > >>>> Any thoughts on this version since our last conversation on V1? >>> >>> Just to let you know that I'm not ignoring this, and I'm trying to >>> formulate a useful response. >> >> Thanks, I had been wondering. >> >> FYI - we've also added another place to make noise about this ECAM >> issue in AMDGPU. This warning should go into 6.9: >> >> https://lore.kernel.org/amd-gfx/20240110101319.695169-1-Jun.Ma2@amd.com/ > > Looks similar to the PCI core warning here: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/probe.c?id=v6.7#n1134 > > The comment says it doesn't work for devices on the root bus, though. > Maybe it could be made to work there as well? IMO it's not loud enough either. I think it's better to keep the both, here's my logic: If someone has this problem that prompted this series the first thing they notice is problems "with the GPU". They'll probably start looking at the kernel log for ERR and WARN related to the GPU. > >>> mmconfig-shared.c has grown into an >>> extremely complicated mess and is a continual source of problems, so >>> I'd really like to untangle it a tiny bit if we can. >>> >>> One thing is that per spec, ACPI motherboard resources are the ONLY >>> way to reserve ECAM space. I'd like to reclaim a little clarity about >>> that and separate out the E820 and EFI stuff as secondary hacks. But >>> there's an insane amount of history that got us here. >> >> I guess you know better than anyone here. But if my idea is >> actually viable then the E820 and EFI stuff turn into "information >> only". > > That would definitely be a good thing. I would like it if that were > more obvious from reading the code because I spend waaay too much time > staring at that labyrinth. > >>> The problem we have to avoid is assigning a BAR that overlaps ECAM. >>> We assign BARs for lots of reasons. dGPU and resizable BARs are >>> examples but there are others, like hotplug and SR-IOV. The fact that >>> Windows works is a red herring because it allocates BARs differently. >> >> Have we actually observed a case that assigning the BAR overlaps >> ECAM region thus far or it's hypothetical? > > Yes, it has happened. There's an example in the commit log here: > https://git.kernel.org/linus/070909e56a7d ("x86/pci: Reserve ECAM if > BIOS didn't include it in PNP0C02 _CRS") But so in this case; if there was a full ECAM reservation made from MMCFG instead then Linux wouldn't have tried to put it on top of that space. > >>> And of course, if there's any way to solve this safely without >>> adding yet another kernel parameter, that would be vastly >>> preferable. >> >> The kernel isn't static though; something we could do is keep the >> parameter around a year or two to get the bug feedback loop of >> people testing it and then rip it out if nothing comes up. > > Yeah. It's pretty hard to remove those options though. For example, > "pci=routeirq" was added in the pre-git era and probably isn't > necessary, but how do we know nobody uses it? Detect it's in use and drop a notice() or higher into the logs like this: "pci=irq has been deprecated and is planned to be removed from the kernel on YY/ZZZZ. If you need this for your system to work, please raise an email to linux-pci@vger.kernel.org" If you give it ~2 years, that gives enough time to get through about 2 LTS kernels. People who need it by then but chose not to report it still have several LTS kernels to fall back on.
[+cc Ivan in case there's opportunity to improve FWTS] On Wed, Jan 17, 2024 at 11:53:50AM -0600, Mario Limonciello wrote: > On 12/15/2023 16:03, Mario Limonciello wrote: > > commit 7752d5cfe3d1 ("x86: validate against acpi motherboard resources") > > introduced checks for ensuring that MCFG table also has memory region > > reservations to ensure no conflicts were introduced from a buggy BIOS. > > > > This has proceeded over time to add other types of reservation checks > > for ACPI PNP resources and EFI MMIO memory type. The PCI firmware spec > > does say that these checks are only required when the operating system > > doesn't comprehend the firmware region: > > > > ``` > > If the operating system does not natively comprehend reserving the MMCFG > > region, the MMCFG region must be reserved by firmware. The address range > > reported in the MCFG table or by _CBA method (see Section 4.1.3) must be > > reserved by declaring a motherboard resource. For most systems, the > > motherboard resource would appear at the root of the ACPI namespace > > (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources > > in this case should not be claimed in the root PCI bus’s _CRS. The > > resources can optionally be returned in Int15 E820h or EFIGetMemoryMap > > as reserved memory but must always be reported through ACPI as a > > motherboard resource. > > ``` > > > > Running this check causes problems with accessing extended PCI > > configuration space on OEM laptops that don't specify the region in PNP > > resources or in the EFI memory map. That later manifests as problems with > > dGPU and accessing resizable BAR. Similar problems don't exist in Windows > > 11 with exact same laptop/firmware stack. > > > > Due to the stability of the Windows ecosystem that x86 machines participate > > it is unlikely that using the region specified in the MCFG table as > > a reservation will cause a problem. The possible worst circumstance could > > be that a buggy BIOS causes a larger hole in the memory map that is > > unusable for devices than intended. > > > > Change the default behavior to keep the region specified in MCFG even if > > it's not specified in another source. This is expected to improve > > machines that otherwise couldn't access PCI extended configuration space. > > > > In case this change causes problems, add a kernel command line parameter > > that can restore the previous behavior. > > > > Link: https://members.pcisig.com/wg/PCI-SIG/document/15350 > > PCI Firmware Specification 3.3 > > Section 4.1.2 MCFG Table Description Note 2 > > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> > > --- > > Bjorn, > > Any thoughts on this version since our last conversation on V1? I really want to clarify the dmesg logging such that it's clear that PNP0C02 reservation is the only valid way to reserve the space described by MCFG. Obviously we have to retain the fallbacks, but I think there should be FW_BUG logging in that case. We currently only do FW_INFO for missing PNP0C02 reservations. I think we should try to change FWTS so it validates MCFG addresses against the PNP0C02 reservations required by spec, instead of searching E820 for them. The spec doesn't require MCFG regions to be in E820, and I think searching there encourages the wrong behavior. It probably also doesn't work at all on arm64, since it doesn't have E820 at all. The /sys/devices/pnp0/00:xx/resources files and "system 00:xx: [mem ..] has been reserved" lines in dmesg would be much better places to check. Bjorn
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 65731b060e3f..eacd0c0521c2 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1473,6 +1473,12 @@ (in particular on some ATI chipsets). The kernel tries to set a reasonable default. + enforce_ecam_resv [X86] + Enforce requiring an ECAM reservation specified in + BIOS for PCI devices. + This parameter is only valid if CONFIG_PCI_MMCONFIG + is enabled. + enforcing= [SELINUX] Set initial enforcing status. Format: {"0" | "1"} See security/selinux/Kconfig help text. diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 0cc9520666ef..aee117c6bbf9 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -34,6 +34,15 @@ static DEFINE_MUTEX(pci_mmcfg_lock); LIST_HEAD(pci_mmcfg_list); +static bool enforce_ecam_resv __read_mostly; +static int __init parse_ecam_options(char *str) +{ + enforce_ecam_resv = true; + + return 1; +} +__setup("enforce_ecam_resv", parse_ecam_options); + static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) { if (cfg->res.parent) @@ -569,10 +578,12 @@ static void __init pci_mmcfg_reject_broken(int early) list_for_each_entry(cfg, &pci_mmcfg_list, list) { if (!pci_mmcfg_reserved(NULL, cfg, early)) { - pr_info("not using ECAM (%pR not reserved)\n", - &cfg->res); - free_all_mmcfg(); - return; + pr_info("ECAM %pR not reserved, %s\n", &cfg->res, + enforce_ecam_resv ? "ignoring" : "using anyway"); + if (enforce_ecam_resv) { + free_all_mmcfg(); + return; + } } } }