diff mbox series

[v1,06/10] arm64: dts: rockchip: add USBDP phys on rk3588

Message ID 20240209181831.104687-7-sebastian.reichel@collabora.com
State New
Headers
Series RK3588 USBDP support |

Commit Message

Sebastian Reichel Feb. 9, 2024, 6:17 p.m. UTC 
  Add both USB3-Displayport PHYs to RK3588 SoC DT.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 62 +++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 73 +++++++++++++++++++++++
 2 files changed, 135 insertions(+)

Comments

Johan Jonker Feb. 11, 2024, 7:24 p.m. UTC | #1 
On 2/9/24 19:17, Sebastian Reichel wrote:
> Add both USB3-Displayport PHYs to RK3588 SoC DT.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 62 +++++++++++++++++++
>  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 73 +++++++++++++++++++++++
>  2 files changed, 135 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 5519c1430cb7..c26288ec75ce 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -17,6 +17,37 @@ pipe_phy1_grf: syscon@fd5c0000 {
>  		reg = <0x0 0xfd5c0000 0x0 0x100>;
>  	};
>  
> +	usbdpphy1_grf: syscon@fd5cc000 {
> +		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> +		reg = <0x0 0xfd5cc000 0x0 0x4000>;
> +	};
> +
> +	usb2phy1_grf: syscon@fd5d4000 {

> +		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> +			     "simple-mfd";

Use same line like usb2phy2_grf.

> +		reg = <0x0 0xfd5d4000 0x0 0x4000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +

> +		u2phy1: usb2-phy@4000 {

        "usb2phy@[0-9a-f]+$":

> +			compatible = "rockchip,rk3588-usb2phy";
> +			reg = <0x4000 0x10>;
> +			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;

> +			resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
> +			reset-names = "phy", "apb";
> +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> +			clock-names = "phyclk";
> +			clock-output-names = "usb480m_phy1";
> +			#clock-cells = <0>;

Align with the (new) documentation
about property ordering.

> +			status = "disabled";
> +
> +			u2phy1_otg: otg-port {
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
>  	i2s8_8ch: i2s@fddc8000 {
>  		compatible = "rockchip,rk3588-i2s-tdm";
>  		reg = <0x0 0xfddc8000 0x0 0x1000>;
> @@ -310,6 +341,37 @@ sata-port@0 {
>  		};
>  	};
>  
> +	usbdp_phy1: phy@fed90000 {
> +		compatible = "rockchip,rk3588-usbdp-phy";
> +		reg = <0x0 0xfed90000 0x0 0x10000>;

> +		rockchip,u2phy-grf = <&usb2phy1_grf>;
> +		rockchip,usb-grf = <&usb_grf>;
> +		rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
> +		rockchip,vo-grf = <&vo0_grf>;
> +		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> +			 <&cru CLK_USBDP_PHY1_IMMORTAL>,
> +			 <&cru PCLK_USBDPPHY1>,
> +			 <&u2phy1>;
> +		clock-names = "refclk", "immortal", "pclk", "utmi";
> +		resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
> +			 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
> +			 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
> +			 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
> +			 <&cru SRST_P_USBDPPHY1>;
> +		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";

Align with the (new) documentation
about property ordering.

> +		status = "disabled";
> +
> +		usbdp_phy1_dp: dp-port {
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		usbdp_phy1_u3: usb3-port {
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +	};
> +
>  	combphy1_ps: phy@fee10000 {
>  		compatible = "rockchip,rk3588-naneng-combphy";
>  		reg = <0x0 0xfee10000 0x0 0x100>;
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 36b1b7acfe6a..553e1883cfe4 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -536,6 +536,37 @@ pipe_phy2_grf: syscon@fd5c4000 {
>  		reg = <0x0 0xfd5c4000 0x0 0x100>;
>  	};
>  
> +	usbdpphy0_grf: syscon@fd5c8000 {
> +		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> +		reg = <0x0 0xfd5c8000 0x0 0x4000>;
> +	};
> +
> +	usb2phy0_grf: syscon@fd5d0000 {

> +		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> +			     "simple-mfd";

Use same line like usb2phy2_grf.

> +		reg = <0x0 0xfd5d0000 0x0 0x4000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +

> +		u2phy0: usb2-phy@0 {

From grf.yaml:

        "usb2phy@[0-9a-f]+$":

> +			compatible = "rockchip,rk3588-usb2phy";
> +			reg = <0x0 0x10>;
> +			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;

> +			resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
> +			reset-names = "phy", "apb";
> +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> +			clock-names = "phyclk";
> +			clock-output-names = "usb480m_phy0";
> +			#clock-cells = <0>;

Align with the (new) documentation
about property ordering.

> +			status = "disabled";
> +
> +			u2phy0_otg: otg-port {
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
>  	usb2phy2_grf: syscon@fd5d8000 {
>  		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";

Fix usb2phy2_grf as well.

        "usb2phy@[0-9a-f]+$":

>  		reg = <0x0 0xfd5d8000 0x0 0x4000>;
> @@ -561,6 +592,17 @@ u2phy2_host: host-port {
>  		};
>  	};
>  
> +	vo0_grf: syscon@fd5a6000 {
> +		compatible = "rockchip,rk3588-vo-grf", "syscon";
> +		reg = <0x0 0xfd5a6000 0x0 0x2000>;
> +		clocks = <&cru PCLK_VO0GRF>;
> +	};
> +
> +	usb_grf: syscon@fd5ac000 {
> +		compatible = "rockchip,rk3588-usb-grf", "syscon";
> +		reg = <0x0 0xfd5ac000 0x0 0x4000>;
> +	};
> +
>  	usb2phy3_grf: syscon@fd5dc000 {
>  		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";

Fix usb2phy3_grf as well.

        "usb2phy@[0-9a-f]+$":


>  		reg = <0x0 0xfd5dc000 0x0 0x4000>;
> @@ -2360,6 +2402,37 @@ dmac2: dma-controller@fed10000 {
>  		#dma-cells = <1>;
>  	};
>  
> +	usbdp_phy0: phy@fed80000 {
> +		compatible = "rockchip,rk3588-usbdp-phy";
> +		reg = <0x0 0xfed80000 0x0 0x10000>;

> +		rockchip,u2phy-grf = <&usb2phy0_grf>;
> +		rockchip,usb-grf = <&usb_grf>;
> +		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
> +		rockchip,vo-grf = <&vo0_grf>;
> +		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> +			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
> +			 <&cru PCLK_USBDPPHY0>,
> +			 <&u2phy0>;
> +		clock-names = "refclk", "immortal", "pclk", "utmi";
> +		resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
> +			 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
> +			 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
> +			 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
> +			 <&cru SRST_P_USBDPPHY0>;
> +		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";

Align with the (new) documentation
about property ordering.

> +		status = "disabled";
> +
> +		usbdp_phy0_dp: dp-port {
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		usbdp_phy0_u3: usb3-port {
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +	};
> +
>  	combphy0_ps: phy@fee00000 {
>  		compatible = "rockchip,rk3588-naneng-combphy";
>  		reg = <0x0 0xfee00000 0x0 0x100>;
Sebastian Reichel Feb. 12, 2024, 6:48 p.m. UTC | #2 
Hi Johan,

On Sun, Feb 11, 2024 at 08:24:36PM +0100, Johan Jonker wrote:
> > +		u2phy1: usb2-phy@4000 {
> 
>         "usb2phy@[0-9a-f]+$":

Interesting. I would have expected that to pop up in dtbs_check, but
it does not for some reason. I will fix it for all usb2phy instances
in rk3588.

> > +			compatible = "rockchip,rk3588-usb2phy";
> > +			reg = <0x4000 0x10>;
> > +			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
> 
> > +			resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
> > +			reset-names = "phy", "apb";
> > +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> > +			clock-names = "phyclk";
> > +			clock-output-names = "usb480m_phy1";
> > +			#clock-cells = <0>;
> 
> Align with the (new) documentation
> about property ordering.
>
> > +			status = "disabled";
> > +
> > +			u2phy1_otg: otg-port {
> > +				#phy-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +	};

The above follows everything from [0], which does not specify an
order for the "standard/common  properties". For those this follows
the order of existing usb2phy nodes. Did I miss any other new
Documentation?

[0] https://www.kernel.org/doc/html/next/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node

-- Sebastian
Johan Jonker Feb. 12, 2024, 10:44 p.m. UTC | #3 
On 2/12/24 19:48, Sebastian Reichel wrote:
> Hi Johan,
> 
> On Sun, Feb 11, 2024 at 08:24:36PM +0100, Johan Jonker wrote:
>>> +		u2phy1: usb2-phy@4000 {
>>
>>         "usb2phy@[0-9a-f]+$":
> 
> Interesting. I would have expected that to pop up in dtbs_check, but
> it does not for some reason. I will fix it for all usb2phy instances
> in rk3588.
> 
>>> +			compatible = "rockchip,rk3588-usb2phy";
>>> +			reg = <0x4000 0x10>;
>>> +			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
>>
>>> +			resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
>>> +			reset-names = "phy", "apb";
>>> +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
>>> +			clock-names = "phyclk";
>>> +			clock-output-names = "usb480m_phy1";
>>> +			#clock-cells = <0>;
>>
>> Align with the (new) documentation
>> about property ordering.
>>
>>> +			status = "disabled";
>>> +
>>> +			u2phy1_otg: otg-port {
>>> +				#phy-cells = <0>;
>>> +				status = "disabled";
>>> +			};
>>> +		};
>>> +	};
> 
> The above follows everything from [0], which does not specify an
> order for the "standard/common  properties". For those this follows
> the order of existing usb2phy nodes. Did I miss any other new
> Documentation?
> 
> [0] https://www.kernel.org/doc/html/next/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node

While reading the text below I think it's in need for a clarification that the property order for common and vendor category is alpha-numerical as is for nodes.
For Rockchip DT in this case "reset*" below "clock*", so that the person after you can add properties in a sort list.

Johan

===

The following order of properties in device nodes is preferred:

    "compatible"

    "reg"

    "ranges"

    Standard/common properties (defined by common bindings, e.g. without vendor-prefixes)

    Vendor-specific properties

    "status" (if applicable)

    Child nodes, where each node is preceded with a blank line

The "status" property is by default "okay", thus it can be omitted.


> 
> -- Sebastian
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 5519c1430cb7..c26288ec75ce 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -17,6 +17,37 @@  pipe_phy1_grf: syscon@fd5c0000 {
 		reg = <0x0 0xfd5c0000 0x0 0x100>;
 	};
 
+	usbdpphy1_grf: syscon@fd5cc000 {
+		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+		reg = <0x0 0xfd5cc000 0x0 0x4000>;
+	};
+
+	usb2phy1_grf: syscon@fd5d4000 {
+		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+			     "simple-mfd";
+		reg = <0x0 0xfd5d4000 0x0 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy1: usb2-phy@4000 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x4000 0x10>;
+			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+			resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+			reset-names = "phy", "apb";
+			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy1";
+			#clock-cells = <0>;
+			status = "disabled";
+
+			u2phy1_otg: otg-port {
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+	};
+
 	i2s8_8ch: i2s@fddc8000 {
 		compatible = "rockchip,rk3588-i2s-tdm";
 		reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +341,37 @@  sata-port@0 {
 		};
 	};
 
+	usbdp_phy1: phy@fed90000 {
+		compatible = "rockchip,rk3588-usbdp-phy";
+		reg = <0x0 0xfed90000 0x0 0x10000>;
+		rockchip,u2phy-grf = <&usb2phy1_grf>;
+		rockchip,usb-grf = <&usb_grf>;
+		rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+		rockchip,vo-grf = <&vo0_grf>;
+		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+			 <&cru CLK_USBDP_PHY1_IMMORTAL>,
+			 <&cru PCLK_USBDPPHY1>,
+			 <&u2phy1>;
+		clock-names = "refclk", "immortal", "pclk", "utmi";
+		resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+			 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
+			 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
+			 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+			 <&cru SRST_P_USBDPPHY1>;
+		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+		status = "disabled";
+
+		usbdp_phy1_dp: dp-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usbdp_phy1_u3: usb3-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+	};
+
 	combphy1_ps: phy@fee10000 {
 		compatible = "rockchip,rk3588-naneng-combphy";
 		reg = <0x0 0xfee10000 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 36b1b7acfe6a..553e1883cfe4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -536,6 +536,37 @@  pipe_phy2_grf: syscon@fd5c4000 {
 		reg = <0x0 0xfd5c4000 0x0 0x100>;
 	};
 
+	usbdpphy0_grf: syscon@fd5c8000 {
+		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+		reg = <0x0 0xfd5c8000 0x0 0x4000>;
+	};
+
+	usb2phy0_grf: syscon@fd5d0000 {
+		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+			     "simple-mfd";
+		reg = <0x0 0xfd5d0000 0x0 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy0: usb2-phy@0 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x0 0x10>;
+			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+			resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+			reset-names = "phy", "apb";
+			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy0";
+			#clock-cells = <0>;
+			status = "disabled";
+
+			u2phy0_otg: otg-port {
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+	};
+
 	usb2phy2_grf: syscon@fd5d8000 {
 		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xfd5d8000 0x0 0x4000>;
@@ -561,6 +592,17 @@  u2phy2_host: host-port {
 		};
 	};
 
+	vo0_grf: syscon@fd5a6000 {
+		compatible = "rockchip,rk3588-vo-grf", "syscon";
+		reg = <0x0 0xfd5a6000 0x0 0x2000>;
+		clocks = <&cru PCLK_VO0GRF>;
+	};
+
+	usb_grf: syscon@fd5ac000 {
+		compatible = "rockchip,rk3588-usb-grf", "syscon";
+		reg = <0x0 0xfd5ac000 0x0 0x4000>;
+	};
+
 	usb2phy3_grf: syscon@fd5dc000 {
 		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xfd5dc000 0x0 0x4000>;
@@ -2360,6 +2402,37 @@  dmac2: dma-controller@fed10000 {
 		#dma-cells = <1>;
 	};
 
+	usbdp_phy0: phy@fed80000 {
+		compatible = "rockchip,rk3588-usbdp-phy";
+		reg = <0x0 0xfed80000 0x0 0x10000>;
+		rockchip,u2phy-grf = <&usb2phy0_grf>;
+		rockchip,usb-grf = <&usb_grf>;
+		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+		rockchip,vo-grf = <&vo0_grf>;
+		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
+			 <&cru PCLK_USBDPPHY0>,
+			 <&u2phy0>;
+		clock-names = "refclk", "immortal", "pclk", "utmi";
+		resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
+			 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
+			 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
+			 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+			 <&cru SRST_P_USBDPPHY0>;
+		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+		status = "disabled";
+
+		usbdp_phy0_dp: dp-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usbdp_phy0_u3: usb3-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+	};
+
 	combphy0_ps: phy@fee00000 {
 		compatible = "rockchip,rk3588-naneng-combphy";
 		reg = <0x0 0xfee00000 0x0 0x100>;