Message ID | 20240207224001.2109224-1-quic_abchauha@quicinc.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-57266-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2547153dyb; Wed, 7 Feb 2024 14:40:44 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVNqF8tdbw6kvp1fJFz5h9rYgxrgCvQRr16cRNN/KZVQI0+QRwEJh5k98TvBWE+fDAosxMCukaeR4j5gQL36imSK8+j9g== X-Google-Smtp-Source: AGHT+IEqWUWEx3NTuyXvNKZMach+4bSncGq34Ra0vlvNdWJ8GjSjlUsbAgq2N+QetoCnUDeid2ml X-Received: by 2002:ac8:5bd4:0:b0:42c:41bd:329c with SMTP id b20-20020ac85bd4000000b0042c41bd329cmr2372923qtb.0.1707345643839; Wed, 07 Feb 2024 14:40:43 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707345643; cv=pass; d=google.com; s=arc-20160816; b=fNj+kVdXfKumqcqFKW2IGTIpUfU3n1Pi0NXG6eyzbNNSf3CyH7Xu5pu3BRvEWEx8m+ Kl6X9ZwLItNuRYCZqBCQzHraaBkVrixNcwIsYOP9fFnYyEOlDAN3hJmWeiP7klZ7gipJ tAQniPStn5MfzSl3+zOZDYvwwXDRe/f+pO/GAuPZW7TD68umQChcor5NdbxkSxy4qVZv R3evOKJbkT+D6e0VZ4EDtAC5lU+2fKYnbSSM9moAHtl/KJSBPQwVvoqjhKNJSIzVNQyf bo8O6v6tVBwZBqwhWWSWWzN3SBu7klJOuTaKPw2a/q62w8HDw6yAzPd2Pd8Wrn75Z8L8 ECxQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature; bh=e8IsPVmgS02K5pCUVYuTMXKVbfZtogBhFG4sXIhGNwI=; fh=57mankyqHLUk4EZ9EUa71B/3ZJ9UTkhuis11FdzsfTE=; b=e9sqj0FC77dOiToUzcgwN+KUPIz3bWAIf2PP7fDNc/vhJstqFnxK1mdeMZr/XlQBTF gRMMPP9b4mm4arcEmVEzbgsznAZJJ2tbPgHVRKjLWmATsrr5kritWcUI8P8nVMpMtkon N4F5YHcvj99PMzKBuv4TGwdmccdFDbkX+ADAIBBDdj4gIl5Cw86LXhpkhyR9aH5J06Mg w1KsgutK8B6rOPObpCzjWWILOqMcbk79W3hfPch2i9la/WxgP7onfQ7Xqdn004klvwf2 iuVhuXuBZ4b4xwQWHu1lFyCDXE9ZREaFpco8PO0woQwl8Z86Fms8HW2AbewwuEUie4S8 gIAA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=R9C+9KFf; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-57266-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57266-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com X-Forwarded-Encrypted: i=2; AJvYcCVXktxOaFTc0VgLCF09BvUZklfNGTCzh8lUcv1XZccouIZwldUtqc6mTWJo9KfEdRgi4zrhNEpTv+1hG1Fcm1s8M//YGA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id x12-20020a05622a000c00b0042c44389c11si1409202qtw.363.2024.02.07.14.40.43 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 14:40:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-57266-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=R9C+9KFf; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-57266-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57266-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 91B9E1C22384 for <ouuuleilei@gmail.com>; Wed, 7 Feb 2024 22:40:43 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C254F1EB40; Wed, 7 Feb 2024 22:40:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="R9C+9KFf" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20D0C1CF8F; Wed, 7 Feb 2024 22:40:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707345623; cv=none; b=VnyejI7ZKANSOF3bFY1eGtQ+2MSS/gwi43jRaPWOWDFUY1+c5AteAF3KtntaSjsPUq/7SH3rtFyKy4BVsFD7EUDIj/eqYMAzg5aj9oVjvRw7WTYG7GG56IbiXQWsWntEMPh1DMUmaH2YARzFAZTIDkTmUr8xXpYgk132HwQZ0ZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707345623; c=relaxed/simple; bh=JrHrLoJ85hFFk3+8HWDc7rX+xkKwsD9tAa8cHPn3WYs=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=ZElVmC+iVPgG58WgZb99CgNRw15Pjc5guj7QDiJnfSCRdRT/cNwP4vyK/B1k9snxibTcqO1Y+v+fOB7PSSbwGIWbfjWELHkOgGCNNZTIvK5/PsKLqBq+WD8JH8tos15gRD2vobDzZCLWlnoapHqGNC5f4IiqgZ/WCfCSCdKvghY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=R9C+9KFf; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 417MaNCb031282; Wed, 7 Feb 2024 22:40:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=qcppdkim1; bh=e8IsPVmgS02K5pCUVYuT MXKVbfZtogBhFG4sXIhGNwI=; b=R9C+9KFfow99zushQ5JA9lx4DAkKwj/on5rG hkes4Kig9Z1f+IFQft1b9VVaIu6CfGJL2QUp074Io8N1jonggDWaGsMcjx78fo/Q EyGfNNRzl/BztRqyYvIX2KcQSonF880z70DA9woelnDCplMxeQoD8+Uy0MO94Tlv 2cD8z673DaX22AMMudIZriNTcqFE3J+vmjIE5lOi2VzzmZqslD5rAEFzPfERLeTj 5jpwRetaJJZK1QTySEV4zQF4hl/s5pvzrTDIO4qzA/ysSvowGLVZpOOQgfIWr33o eb6TlE7PnFNG0ezAOfvuFks+jG+GrF3nVEx2ZyYbNMRrY/Xe7Q== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w4hhk85hh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Feb 2024 22:40:03 +0000 (GMT) Received: from pps.filterd (NALASPPMTA04.qualcomm.com [127.0.0.1]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 417Me284024292; Wed, 7 Feb 2024 22:40:02 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA04.qualcomm.com (PPS) with ESMTPS id 3w47rjkww5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Feb 2024 22:40:02 +0000 Received: from NALASPPMTA04.qualcomm.com (NALASPPMTA04.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 417Me2Si024265; Wed, 7 Feb 2024 22:40:02 GMT Received: from hu-devc-lv-u20-a-new.qualcomm.com (hu-abchauha-lv.qualcomm.com [10.81.25.35]) by NALASPPMTA04.qualcomm.com (PPS) with ESMTPS id 417Me1Sg024240 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Feb 2024 22:40:02 +0000 Received: by hu-devc-lv-u20-a-new.qualcomm.com (Postfix, from userid 214165) id BA973220E1; Wed, 7 Feb 2024 14:40:01 -0800 (PST) From: Abhishek Chauhan <quic_abchauha@quicinc.com> To: Alexandre Torgue <alexandre.torgue@foss.st.com>, Jose Abreu <joabreu@synopsys.com>, "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Halaney <ahalaney@redhat.com>, Jeff Johnson <quic_jjohnson@quicinc.com> Cc: kernel@quicinc.com Subject: [PATCH net-next v3] net: stmmac: dwmac-qcom-ethqos: Enable TBS on all queues but 0 Date: Wed, 7 Feb 2024 14:40:01 -0800 Message-Id: <20240207224001.2109224-1-quic_abchauha@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: CUSyoBKPajMxG-bRe_wXkb7umQSdrnsz X-Proofpoint-GUID: CUSyoBKPajMxG-bRe_wXkb7umQSdrnsz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-07_09,2024-02-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=819 spamscore=0 adultscore=0 phishscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402070167 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790281666014967070 X-GMAIL-MSGID: 1790281666014967070 |
Series |
[net-next,v3] net: stmmac: dwmac-qcom-ethqos: Enable TBS on all queues but 0
|
|
Commit Message
Abhishek Chauhan
Feb. 7, 2024, 10:40 p.m. UTC
TSO and TBS cannot co-exist. TBS requires special descriptor to be
allocated at bootup. Initialising Tx queues at probe to support
TSO and TBS can help in allocating those resources at bootup.
TX queues with TBS can support etf qdisc hw offload.
This is similar to the patch raised by NXP
commit 3b12ec8f618e ("net: stmmac: dwmac-imx: set TSO/TBS TX queues default
settings")
Changes since v2:
- Fixed the styling of comment in the dwmac-qcom-ethqos.c
- Followed the upstream format to give other glue
driver references to solve the same problem
- Appended the subject with net-next
- Discussion of why this patch is required is discussed in
https://lore.kernel.org/netdev/c2497eef-1041-4cd0-8220-42622c8902f4@quicinc.com/
Changes since v1:
- Subject is changed as per upstream guidelines
- Added a reference of a similar change done by NXP in
body of the commit message
Signed-off-by: Abhishek Chauhan <quic_abchauha@quicinc.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
Comments
On 2/7/2024 2:40 PM, Abhishek Chauhan wrote: > TSO and TBS cannot co-exist. TBS requires special descriptor to be > allocated at bootup. Initialising Tx queues at probe to support > TSO and TBS can help in allocating those resources at bootup. > > TX queues with TBS can support etf qdisc hw offload. > > This is similar to the patch raised by NXP > commit 3b12ec8f618e ("net: stmmac: dwmac-imx: set TSO/TBS TX queues default > settings") > > Changes since v2: > - Fixed the styling of comment in the dwmac-qcom-ethqos.c > - Followed the upstream format to give other glue > driver references to solve the same problem > - Appended the subject with net-next > - Discussion of why this patch is required is discussed in > https://lore.kernel.org/netdev/c2497eef-1041-4cd0-8220-42622c8902f4@quicinc.com/ > > Changes since v1: > - Subject is changed as per upstream guidelines > - Added a reference of a similar change done by NXP in > body of the commit message Note that your patch change history should not be part of your commit text, but instead should be below the "---" line. > > Signed-off-by: Abhishek Chauhan <quic_abchauha@quicinc.com> > --- in other words put it here. the change history will not be part of the git history I strongly suggest looking at b4 since it will manage your patch history: https://b4.docs.kernel.org/en/latest/index.html#for-developers > drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > index 31631e3f89d0..2691a250a5a7 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > @@ -728,7 +728,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) > struct stmmac_resources stmmac_res; > struct device *dev = &pdev->dev; > struct qcom_ethqos *ethqos; > - int ret; > + int ret, i; > > ret = stmmac_get_platform_resources(pdev, &stmmac_res); > if (ret) > @@ -822,6 +822,10 @@ static int qcom_ethqos_probe(struct platform_device *pdev) > plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; > } > > + /* Enable TSO on queue0 and enable TBS on rest of the queues */ > + for (i = 1; i < plat_dat->tx_queues_to_use; i++) > + plat_dat->tx_queues_cfg[i].tbs_en = 1; > + > return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); > } >
On Wed, Feb 07, 2024 at 02:40:01PM -0800, Abhishek Chauhan wrote: > TSO and TBS cannot co-exist. TBS requires special descriptor to be > allocated at bootup. Initialising Tx queues at probe to support > TSO and TBS can help in allocating those resources at bootup. > > TX queues with TBS can support etf qdisc hw offload. > > This is similar to the patch raised by NXP > commit 3b12ec8f618e ("net: stmmac: dwmac-imx: set TSO/TBS TX queues default > settings") > > Changes since v2: > - Fixed the styling of comment in the dwmac-qcom-ethqos.c > - Followed the upstream format to give other glue > driver references to solve the same problem > - Appended the subject with net-next > - Discussion of why this patch is required is discussed in > https://lore.kernel.org/netdev/c2497eef-1041-4cd0-8220-42622c8902f4@quicinc.com/ > > Changes since v1: > - Subject is changed as per upstream guidelines > - Added a reference of a similar change done by NXP in > body of the commit message > > Signed-off-by: Abhishek Chauhan <quic_abchauha@quicinc.com> Please add my: Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride when submitting v4 with the changelog moved as Jeff mentioned. This seems to work well (I can enable ETF on all queues but 0, and as far as I can tell after trying to test that for a while it seems to work as expected). Thanks, Andrew > --- > drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > index 31631e3f89d0..2691a250a5a7 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c > @@ -728,7 +728,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) > struct stmmac_resources stmmac_res; > struct device *dev = &pdev->dev; > struct qcom_ethqos *ethqos; > - int ret; > + int ret, i; > > ret = stmmac_get_platform_resources(pdev, &stmmac_res); > if (ret) > @@ -822,6 +822,10 @@ static int qcom_ethqos_probe(struct platform_device *pdev) > plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; > } > > + /* Enable TSO on queue0 and enable TBS on rest of the queues */ > + for (i = 1; i < plat_dat->tx_queues_to_use; i++) > + plat_dat->tx_queues_cfg[i].tbs_en = 1; > + > return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); > } > > -- > 2.25.1 >
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 31631e3f89d0..2691a250a5a7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -728,7 +728,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) struct stmmac_resources stmmac_res; struct device *dev = &pdev->dev; struct qcom_ethqos *ethqos; - int ret; + int ret, i; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) @@ -822,6 +822,10 @@ static int qcom_ethqos_probe(struct platform_device *pdev) plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; } + /* Enable TSO on queue0 and enable TBS on rest of the queues */ + for (i = 1; i < plat_dat->tx_queues_to_use; i++) + plat_dat->tx_queues_cfg[i].tbs_en = 1; + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); }