[v8,03/13] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag
Message ID | 166759201032.3281208.8545863740733338256.stgit@bmoger-ubuntu |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp609229wru; Fri, 4 Nov 2022 13:01:43 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Xq8ltrZn+ksJcd3JHppGRCulNc4Bh2xW2NXYHVIdFKDMT7F+BA/CpkCxDx4cfQspYTf0L X-Received: by 2002:a17:902:b581:b0:186:fb90:1151 with SMTP id a1-20020a170902b58100b00186fb901151mr36945713pls.43.1667592102822; Fri, 04 Nov 2022 13:01:42 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1667592102; cv=pass; d=google.com; s=arc-20160816; b=Tdwl87evrpFojAOkT3e0++93z+KiMRPi5DUMKYGS87afYeXDbF9PddwBSha+YeiE2j 78eHMsM90XIDY+c7trNQuUCoCKnvJuzZgEvGiOrM8JXwIjwvXSvxHSHUQDrNoTfpfA7T Roevgs1izu2jy+E4Fn29faMAeS81HHNG77Uooh+HbFvpLGSM2p+IxivAAUCI2YkPlW8V BBPIAlQgo5AJC/4/RMhNY9kmQczBRVJbQfyuG0r1yDTxhBe2ZmyspSnuw9RQmHUH1QVX F0SxTpnfeLCauqFp2E+CTpX6u+CUk4wFhhjQaFfMXuFTTC5RMH2e8t7oOhkdeXHuoot2 n2Yw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:cc:to:from :subject:dkim-signature; bh=aS1lU0zXNAUhuu9mwovoNExV1tBWYnCwFelGPZ1pfQA=; b=0PH07/8Qe3opN9PZ1oW+CxUFUZ96RVaIPTg5rkf/YuFL12hnJaOXhS4BA+KnPI/ixO Jrybm4qHP2HABMbUZwNCJeyB3rbNdLYWGAOftHd9vREIm92qUaXY8MM+tZnfTtRTT5Xu sgL3P2kF4YS86t6HmLKHEMXY6Onobki+sWhI7iXmoUqWi6hQ/EP21Z5ffRywasNoExeK LjvT1iBOv4XPGuDYoC5hHiS7z07msqyqE784QsC1qx44igYqzKtGkNYyaNHOWPeNaOpc IHJNJ4g2H2Fi8TK8olN2Zku3f2y7kL0s7Qlw6GXQg++QdDeuc5KKjX/H6NQpiWZrmomN tX7w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=MSd+BvIW; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e13-20020a63500d000000b0046ea4ef43ffsi495728pgb.375.2022.11.04.13.01.28; Fri, 04 Nov 2022 13:01:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=MSd+BvIW; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229499AbiKDUA2 (ORCPT <rfc822;hjfbswb@gmail.com> + 99 others); Fri, 4 Nov 2022 16:00:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229788AbiKDUAV (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 4 Nov 2022 16:00:21 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2086.outbound.protection.outlook.com [40.107.244.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A08845A20; Fri, 4 Nov 2022 13:00:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XGhD+r/2hWWiGNh2fS9yHRtd+IvQVum6Nq3qShs9UcbXhs8hZ6kU7D/6WoyUJJgfNyL+LKUyNTtygERfBu7iv5EUs96Ng0MpYowtl1dupaE9ujgQHoXFEzYevi9oRY93agALx5X6Kzij7LyLBXr9uWZ+n46aS4KN/Bq8p6L7AVm1Z7WlrLA2hJsoK8GmQeX6hF2xLX/8ndy8mJdpsa9iCEbxvlB1xNM+FbXgtlzhzCBDvaGgBVwoE9IzKOhljwoedPrLpLh0vfJQABSeaDEkqmYqk4VC4Fep57qN9L9K9cCifD9UIKP8fqg6DDXNnNauLl+ED4EqMX9nWOjJfJRyyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aS1lU0zXNAUhuu9mwovoNExV1tBWYnCwFelGPZ1pfQA=; b=SwLGWW1vmvV3e0Qksur7yVTvR041ada0K34dRAZ+N9YEOruXi9oaHB92jokjs0KoJ4/rayzcBs4VTOWspA1Kx4zIKFYy2hVIFtgKKamXds0Ab9EsSK7dFzLu7bnjmplRVoOU+t/o3xbfLo/UoBCvAgKktgKsJ4EUQp90gtLSNjMGXYZWZuV47T+wpxGqloYp3Uo/SpAdMGzKkxTlhZ6jtRYdkg/neG57tsqzG9433dgSMBFTZT5pBiln2oljRnrGlj5aAiqlU7kzvyNaMvaK4lplnSHrBuH64EPG7BWeG40tQsbnSLjf9N2iNnMopSoibMh6IUFkccRysRbeJSmMZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=quicinc.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aS1lU0zXNAUhuu9mwovoNExV1tBWYnCwFelGPZ1pfQA=; b=MSd+BvIWBGBRUd1+ecmmR3OvKnKWkgOLRIL0wtW+lxkCjYPpQswSiPfsgYFWKFfQO0t448IafUD8BFTNc0D2rkg+BMww5FbEByyaqOCQ/sz3B2gTNwYTpb5Z+TeGofjQnSPWsr9x7G7h2W7iRK3zmClkHUlSTnaEWROoJQ/Gstg= Received: from DM6PR02CA0146.namprd02.prod.outlook.com (2603:10b6:5:332::13) by PH0PR12MB8125.namprd12.prod.outlook.com (2603:10b6:510:293::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.20; Fri, 4 Nov 2022 20:00:17 +0000 Received: from DM6NAM11FT082.eop-nam11.prod.protection.outlook.com (2603:10b6:5:332:cafe::65) by DM6PR02CA0146.outlook.office365.com (2603:10b6:5:332::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22 via Frontend Transport; Fri, 4 Nov 2022 20:00:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT082.mail.protection.outlook.com (10.13.173.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Fri, 4 Nov 2022 20:00:17 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Fri, 4 Nov 2022 15:00:15 -0500 Subject: [PATCH v8 03/13] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag From: Babu Moger <babu.moger@amd.com> To: <corbet@lwn.net>, <reinette.chatre@intel.com>, <tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de> CC: <fenghua.yu@intel.com>, <dave.hansen@linux.intel.com>, <x86@kernel.org>, <hpa@zytor.com>, <paulmck@kernel.org>, <akpm@linux-foundation.org>, <quic_neeraju@quicinc.com>, <rdunlap@infradead.org>, <damien.lemoal@opensource.wdc.com>, <songmuchun@bytedance.com>, <peterz@infradead.org>, <jpoimboe@kernel.org>, <pbonzini@redhat.com>, <babu.moger@amd.com>, <chang.seok.bae@intel.com>, <pawan.kumar.gupta@linux.intel.com>, <jmattson@google.com>, <daniel.sneddon@linux.intel.com>, <sandipan.das@amd.com>, <tony.luck@intel.com>, <james.morse@arm.com>, <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <bagasdotme@gmail.com>, <eranian@google.com> Date: Fri, 4 Nov 2022 15:00:10 -0500 Message-ID: <166759201032.3281208.8545863740733338256.stgit@bmoger-ubuntu> In-Reply-To: <166759188265.3281208.11769277079826754455.stgit@bmoger-ubuntu> References: <166759188265.3281208.11769277079826754455.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT082:EE_|PH0PR12MB8125:EE_ X-MS-Office365-Filtering-Correlation-Id: dbbb9ac0-38db-47af-e94b-08dabe9f3222 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vGNb2lrg4jquiirc3zSnhBvmJxNY7oZx600M6+fF9EknOHVosZbcBzhf+jEuTRcYuV7IX0X/Xe9y64b2LAheZEkf6qTvZbWwJxLGf4996N6V4++LjBssge55iF+ZQo+tw+g1Y1s0TcJGujjaDORmDFmUbW3LJhraZKieorSxcoCQ3Gbz0Q5oPRO1ySIZsJZbiiKepHea5sjlUOTqr0yXJNo8lil9RgQE4uQtp5I2l9pzXvaffXzE6K8vk41N3McONCXSWaGJS5NOSRcG/rEqDEhNkIeZrbR8PIPHKLvDevtLLd57hc1tJdj18io8SwWatcwba8gxl7OlcSYcJ8SyQTRaZshuJIL5gqk67DPt4wRLpf+xhqbxVnKkYZQJXe34pTWnKd/tmORsKrlCyEWoUP93m1gu6DamxTCAbV+YWl5qRyqGs7ojGXs8MNEuV7QhziFI9vDWJlXf92Fyfgfez/GNsf7u5SHA9I1lhZSKpygxsmf+RhSBZgu//+cW4bX7Cj+dCGFqP1mZOI9nLo1Hk2D7rbLzm2oGGKUxY7g92GQUHJAGBRm5id5xBO/HGnVLpEVrVekfebsR3IWEPKlCWPGW8AcOf/qyC92Bfep622FsGOFdmSb1sqy1ltsd6og+rmiv0jJ39q/vfDCTJBQ6VUebIkB5JLnpNJwt31M4U3B7WQpFamOODmxs9uXi8kd8XSSTnSfrDDAHbzr5MnJi9sXSR5dKvAqpE1RQnFGI7Uvb3DIlkmje/hBcgd+58/0XATr/qiA1Soyy3lt7/kJc24tl4fyXUtcYaWLi1fQqBn8djd7K9gBERAIPm+qJi/fxR8tInCB14e9wG06YZhdnSetZa6imNhLF0/wXWuQZNETZo6VaHAOTFXGgM8Xdziig7jmB3t7zmbkgfBEV293zWg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(7916004)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(46966006)(36840700001)(40470700004)(103116003)(8936002)(966005)(82310400005)(7416002)(2906002)(36860700001)(9686003)(26005)(356005)(81166007)(33716001)(40480700001)(186003)(16526019)(47076005)(5660300002)(86362001)(336012)(82740400003)(40460700003)(478600001)(83380400001)(44832011)(426003)(41300700001)(70206006)(16576012)(4326008)(70586007)(8676002)(316002)(54906003)(6666004)(110136005)(71626007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 20:00:17.5635 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbbb9ac0-38db-47af-e94b-08dabe9f3222 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT082.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8125 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748597056703722993?= X-GMAIL-MSGID: =?utf-8?q?1748597056703722993?= |
Series |
Support for AMD QoS new features
|
|
Commit Message
Moger, Babu
Nov. 4, 2022, 8 p.m. UTC
Newer AMD processors support the new feature Bandwidth Monitoring Event
Configuration (BMEC).
The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=0).
Bits Field Name Description
3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC)
Currently, the bandwidth monitoring events mbm_total_bytes and
mbm_local_bytes are set to count all the total and local reads/writes
respectively. With the introduction of slow memory, the two counters
are not enough to count all the different types of memory events. With
the feature BMEC, the users have the option to configure
mbm_total_bytes and mbm_local_bytes to count the specific type of
events.
Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h +
EventID) which contains one field for each bandwidth type that can be
used to configure the bandwidth event to track any combination of
supported bandwidth types. The event will count requests from every
bandwidth type bit that is set in the corresponding configuration
register.
Following are the types of events supported:
==== ========================================================
Bits Description
==== ========================================================
6 Dirty Victims from the QOS domain to all types of memory
5 Reads to slow memory in the non-local NUMA domain
4 Reads to slow memory in the local NUMA domain
3 Non-temporal writes to non-local NUMA domain
2 Non-temporal writes to local NUMA domain
1 Reads to memory in the non-local NUMA domain
0 Reads to memory in the local NUMA domain
==== ========================================================
By default, the mbm_total_bytes configuration is set to 0x7F to count
all the event types and the mbm_local_bytes configuration is set to
0x15 to count all the local memory events.
Feature description is available in the specification, "AMD64
Technology Platform Quality of Service Extensions, Revision: 1.03
Publication
Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-quality-service-extensions
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
arch/x86/kernel/cpu/scattered.c | 1 +
3 files changed, 3 insertions(+)
Comments
Hi Babu, On 11/4/2022 1:00 PM, Babu Moger wrote: > Newer AMD processors support the new feature Bandwidth Monitoring Event > Configuration (BMEC). > > The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=0). > Bits Field Name Description > 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) > > Currently, the bandwidth monitoring events mbm_total_bytes and > mbm_local_bytes are set to count all the total and local reads/writes > respectively. With the introduction of slow memory, the two counters > are not enough to count all the different types of memory events. With > the feature BMEC, the users have the option to configure > mbm_total_bytes and mbm_local_bytes to count the specific type of > events. > > Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h + > EventID) which contains one field for each bandwidth type that can be Looking at later patches it seems that it is not really 0xc000_0400h + EventID but instead "0xc000_0400h + index_based_on_EventID"? This may be too much detail for this changelog so maybe these specifics can be deferred and just refer to the "configuration MSR". > used to configure the bandwidth event to track any combination of > supported bandwidth types. The event will count requests from every > bandwidth type bit that is set in the corresponding configuration > register. > > Following are the types of events supported: > > ==== ======================================================== > Bits Description > ==== ======================================================== > 6 Dirty Victims from the QOS domain to all types of memory > 5 Reads to slow memory in the non-local NUMA domain > 4 Reads to slow memory in the local NUMA domain > 3 Non-temporal writes to non-local NUMA domain > 2 Non-temporal writes to local NUMA domain > 1 Reads to memory in the non-local NUMA domain > 0 Reads to memory in the local NUMA domain > ==== ======================================================== > > By default, the mbm_total_bytes configuration is set to 0x7F to count > all the event types and the mbm_local_bytes configuration is set to > 0x15 to count all the local memory events. > > Feature description is available in the specification, "AMD64 > Technology Platform Quality of Service Extensions, Revision: 1.03 > Publication > > Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-quality-service-extensions > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/cpuid-deps.c | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index d68b4c9c181d..6732ca0117be 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -306,6 +306,7 @@ > #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ > #define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth tracking for RSB stuffing */ > #define X86_FEATURE_SMBA (11*32+19) /* Slow Memory Bandwidth Allocation */ > +#define X86_FEATURE_BMEC (11*32+20) /* AMD Bandwidth Monitoring Event Configuration (BMEC) */ Surely a nitpick but it is strange that the two features introduced in this series are described differently. Why does SMBA deserve the "AMD" prefix but BMEC does not? I do not think the "(BMEC)" is necessary since it is in X86_FEATURE_BMEC. > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ > #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ > diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c > index c881bcafba7d..4555f9596ccf 100644 > --- a/arch/x86/kernel/cpu/cpuid-deps.c > +++ b/arch/x86/kernel/cpu/cpuid-deps.c > @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] = { > { X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC }, > { X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC }, > { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, > + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC }, > { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, > { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, > { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index 5a5f17ed69a2..67c4d24e06ef 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, > { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, > { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, > + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, > { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, > { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, > { 0, 0, 0, 0, 0 } > > Reinette
[AMD Official Use Only - General] Hi Reinette, > -----Original Message----- > From: Reinette Chatre <reinette.chatre@intel.com> > Sent: Tuesday, November 22, 2022 6:09 PM > To: Moger, Babu <Babu.Moger@amd.com>; corbet@lwn.net; > tglx@linutronix.de; mingo@redhat.com; bp@alien8.de > Cc: fenghua.yu@intel.com; dave.hansen@linux.intel.com; x86@kernel.org; > hpa@zytor.com; paulmck@kernel.org; akpm@linux-foundation.org; > quic_neeraju@quicinc.com; rdunlap@infradead.org; > damien.lemoal@opensource.wdc.com; songmuchun@bytedance.com; > peterz@infradead.org; jpoimboe@kernel.org; pbonzini@redhat.com; > chang.seok.bae@intel.com; pawan.kumar.gupta@linux.intel.com; > jmattson@google.com; daniel.sneddon@linux.intel.com; Das1, Sandipan > <Sandipan.Das@amd.com>; tony.luck@intel.com; james.morse@arm.com; > linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; > bagasdotme@gmail.com; eranian@google.com > Subject: Re: [PATCH v8 03/13] x86/cpufeatures: Add Bandwidth Monitoring > Event Configuration feature flag > > Hi Babu, > > On 11/4/2022 1:00 PM, Babu Moger wrote: > > Newer AMD processors support the new feature Bandwidth Monitoring > > Event Configuration (BMEC). > > > > The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=0). > > Bits Field Name Description > > 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) > > > > Currently, the bandwidth monitoring events mbm_total_bytes and > > mbm_local_bytes are set to count all the total and local reads/writes > > respectively. With the introduction of slow memory, the two counters > > are not enough to count all the different types of memory events. With > > the feature BMEC, the users have the option to configure > > mbm_total_bytes and mbm_local_bytes to count the specific type of > > events. > > > > Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h + > > EventID) which contains one field for each bandwidth type that can be > > Looking at later patches it seems that it is not really 0xc000_0400h + EventID > but instead "0xc000_0400h + index_based_on_EventID"? This may be too much > detail for this changelog so maybe these specifics can be deferred and just > refer to the "configuration MSR". Sure. > > > used to configure the bandwidth event to track any combination of > > supported bandwidth types. The event will count requests from every > > bandwidth type bit that is set in the corresponding configuration > > register. > > > > Following are the types of events supported: > > > > ==== ======================================================== > > Bits Description > > ==== ======================================================== > > 6 Dirty Victims from the QOS domain to all types of memory > > 5 Reads to slow memory in the non-local NUMA domain > > 4 Reads to slow memory in the local NUMA domain > > 3 Non-temporal writes to non-local NUMA domain > > 2 Non-temporal writes to local NUMA domain > > 1 Reads to memory in the non-local NUMA domain > > 0 Reads to memory in the local NUMA domain > > ==== ======================================================== > > > > By default, the mbm_total_bytes configuration is set to 0x7F to count > > all the event types and the mbm_local_bytes configuration is set to > > 0x15 to count all the local memory events. > > > > Feature description is available in the specification, "AMD64 > > Technology Platform Quality of Service Extensions, Revision: 1.03 > > Publication > > > > Link: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww. > > amd.com%2Fen%2Fsupport%2Ftech-docs%2Famd64-technology-platform- > quality > > -service- > extensions&data=05%7C01%7Cbabu.moger%40amd.com%7Cb1bc7003 > > > 552c454ebd7108dacce701e2%7C3dd8961fe4884e608e11a82d994e183d%7C0% > 7C0%7C > > > 638047589785935363%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD > AiLCJQIjo > > > iV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdat > a=rzAi > > HpRRXRNE37bfTt318tSj4sMhBXftW9inSi30rFk%3D&reserved=0 > > Link: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > > > illa.kernel.org%2Fshow_bug.cgi%3Fid%3D206537&data=05%7C01%7Cbab > u.m > > > oger%40amd.com%7Cb1bc7003552c454ebd7108dacce701e2%7C3dd8961fe488 > 4e608e > > > 11a82d994e183d%7C0%7C0%7C638047589785935363%7CUnknown%7CTWFpb > GZsb3d8ey > > > JWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C300 > > > 0%7C%7C%7C&sdata=ghlUpN23gdyaJ7FZQFGgJTZOgo4LNJaE5JFLa1ezaTw > %3D&am > > p;reserved=0 > > Signed-off-by: Babu Moger <babu.moger@amd.com> > > --- > > arch/x86/include/asm/cpufeatures.h | 1 + > > arch/x86/kernel/cpu/cpuid-deps.c | 1 + > > arch/x86/kernel/cpu/scattered.c | 1 + > > 3 files changed, 3 insertions(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h > > b/arch/x86/include/asm/cpufeatures.h > > index d68b4c9c181d..6732ca0117be 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -306,6 +306,7 @@ > > #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on > VM exit when EIBRS is enabled */ > > #define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth > tracking for RSB stuffing */ > > #define X86_FEATURE_SMBA (11*32+19) /* Slow Memory > Bandwidth Allocation */ > > +#define X86_FEATURE_BMEC (11*32+20) /* AMD > Bandwidth Monitoring Event Configuration (BMEC) */ > > Surely a nitpick but it is strange that the two features introduced in this series > are described differently. Why does SMBA deserve the "AMD" prefix but BMEC > does not? I do not think the "(BMEC)" is necessary since it is in > X86_FEATURE_BMEC. Sure. Wil remove AMD prefix and "BMEC)". Thanks Babu > > > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ > > #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI > instructions */ > > diff --git a/arch/x86/kernel/cpu/cpuid-deps.c > > b/arch/x86/kernel/cpu/cpuid-deps.c > > index c881bcafba7d..4555f9596ccf 100644 > > --- a/arch/x86/kernel/cpu/cpuid-deps.c > > +++ b/arch/x86/kernel/cpu/cpuid-deps.c > > @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] = { > > { X86_FEATURE_CQM_OCCUP_LLC, > X86_FEATURE_CQM_LLC }, > > { X86_FEATURE_CQM_MBM_TOTAL, > X86_FEATURE_CQM_LLC }, > > { X86_FEATURE_CQM_MBM_LOCAL, > X86_FEATURE_CQM_LLC }, > > + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC }, > > { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, > > { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, > > { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES > }, > > diff --git a/arch/x86/kernel/cpu/scattered.c > > b/arch/x86/kernel/cpu/scattered.c index 5a5f17ed69a2..67c4d24e06ef > > 100644 > > --- a/arch/x86/kernel/cpu/scattered.c > > +++ b/arch/x86/kernel/cpu/scattered.c > > @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { > > { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, > > { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, > > { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, > > + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, > > { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, > > { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, > > { 0, 0, 0, 0, 0 } > > > > > > Reinette
Hi, Babu, > Newer AMD processors support the new feature Bandwidth Monitoring Event > Configuration (BMEC). > > The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=0). > Bits Field Name Description > 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) > > Currently, the bandwidth monitoring events mbm_total_bytes and > mbm_local_bytes are set to count all the total and local reads/writes > respectively. With the introduction of slow memory, the two counters are not > enough to count all the different types of memory events. With the feature > BMEC, the users have the option to configure mbm_total_bytes and > mbm_local_bytes to count the specific type of events. > > Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h + > EventID) which contains one field for each bandwidth type that can be used to > configure the bandwidth event to track any combination of supported > bandwidth types. The event will count requests from every bandwidth type bit > that is set in the corresponding configuration register. > > Following are the types of events supported: > > ==== ======================================================== > Bits Description > ==== ======================================================== > 6 Dirty Victims from the QOS domain to all types of memory > 5 Reads to slow memory in the non-local NUMA domain > 4 Reads to slow memory in the local NUMA domain > 3 Non-temporal writes to non-local NUMA domain > 2 Non-temporal writes to local NUMA domain > 1 Reads to memory in the non-local NUMA domain > 0 Reads to memory in the local NUMA domain > ==== ======================================================== > > By default, the mbm_total_bytes configuration is set to 0x7F to count all the > event types and the mbm_local_bytes configuration is set to > 0x15 to count all the local memory events. > > Feature description is available in the specification, "AMD64 Technology > Platform Quality of Service Extensions, Revision: 1.03 Publication > > Link: https://www.amd.com/en/support/tech-docs/amd64-technology- > platform-quality-service-extensions > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/cpuid-deps.c | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index d68b4c9c181d..6732ca0117be 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -306,6 +306,7 @@ > #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM > exit when EIBRS is enabled */ > #define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth > tracking for RSB stuffing */ > #define X86_FEATURE_SMBA (11*32+19) /* Slow Memory > Bandwidth Allocation */ > +#define X86_FEATURE_BMEC (11*32+20) /* AMD Bandwidth > Monitoring Event Configuration (BMEC) */ > > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ > #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI > instructions */ > diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid- > deps.c > index c881bcafba7d..4555f9596ccf 100644 > --- a/arch/x86/kernel/cpu/cpuid-deps.c > +++ b/arch/x86/kernel/cpu/cpuid-deps.c > @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] = { > { X86_FEATURE_CQM_OCCUP_LLC, > X86_FEATURE_CQM_LLC }, > { X86_FEATURE_CQM_MBM_TOTAL, > X86_FEATURE_CQM_LLC }, > { X86_FEATURE_CQM_MBM_LOCAL, > X86_FEATURE_CQM_LLC }, > + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC }, Shouldn't X86_FEATURE_BMEC really depend on X86_FEATURE_CQM_MBM_LOCAL and _TOTAL? CQM_MBM_LOCAL and/or _TOTAL can be disabled but CQM_LLC can still be enabled. In this case, BMEC shouldn't be enabled, right? But with this patch, BMEC will be enabled but it won't work well as CQM_MBM_TOTAL/_LOCAL are not enabled. You may remove the above line and add these two lines: + { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, + { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, Thanks. -Fenghua
[AMD Official Use Only - General] Hi Fenghua, > -----Original Message----- > From: Yu, Fenghua <fenghua.yu@intel.com> > Sent: Wednesday, November 23, 2022 12:17 PM > To: Moger, Babu <Babu.Moger@amd.com>; corbet@lwn.net; Chatre, Reinette > <reinette.chatre@intel.com>; tglx@linutronix.de; mingo@redhat.com; > bp@alien8.de > Cc: dave.hansen@linux.intel.com; x86@kernel.org; hpa@zytor.com; > paulmck@kernel.org; akpm@linux-foundation.org; quic_neeraju@quicinc.com; > rdunlap@infradead.org; damien.lemoal@opensource.wdc.com; > songmuchun@bytedance.com; peterz@infradead.org; jpoimboe@kernel.org; > pbonzini@redhat.com; Bae, Chang Seok <chang.seok.bae@intel.com>; > pawan.kumar.gupta@linux.intel.com; jmattson@google.com; > daniel.sneddon@linux.intel.com; Das1, Sandipan <Sandipan.Das@amd.com>; > Luck, Tony <tony.luck@intel.com>; james.morse@arm.com; linux- > doc@vger.kernel.org; linux-kernel@vger.kernel.org; bagasdotme@gmail.com; > Eranian, Stephane <eranian@google.com> > Subject: RE: [PATCH v8 03/13] x86/cpufeatures: Add Bandwidth Monitoring > Event Configuration feature flag > > Hi, Babu, > > > Newer AMD processors support the new feature Bandwidth Monitoring > > Event Configuration (BMEC). > > > > The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=0). > > Bits Field Name Description > > 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) > > > > Currently, the bandwidth monitoring events mbm_total_bytes and > > mbm_local_bytes are set to count all the total and local reads/writes > > respectively. With the introduction of slow memory, the two counters > > are not enough to count all the different types of memory events. With > > the feature BMEC, the users have the option to configure > > mbm_total_bytes and mbm_local_bytes to count the specific type of events. > > > > Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h + > > EventID) which contains one field for each bandwidth type that can be > > used to configure the bandwidth event to track any combination of > > supported bandwidth types. The event will count requests from every > > bandwidth type bit that is set in the corresponding configuration register. > > > > Following are the types of events supported: > > > > ==== ======================================================== > > Bits Description > > ==== ======================================================== > > 6 Dirty Victims from the QOS domain to all types of memory > > 5 Reads to slow memory in the non-local NUMA domain > > 4 Reads to slow memory in the local NUMA domain > > 3 Non-temporal writes to non-local NUMA domain > > 2 Non-temporal writes to local NUMA domain > > 1 Reads to memory in the non-local NUMA domain > > 0 Reads to memory in the local NUMA domain > > ==== ======================================================== > > > > By default, the mbm_total_bytes configuration is set to 0x7F to count > > all the event types and the mbm_local_bytes configuration is set to > > 0x15 to count all the local memory events. > > > > Feature description is available in the specification, "AMD64 > > Technology Platform Quality of Service Extensions, Revision: 1.03 > > Publication > > > > Link: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww. > > amd.com%2Fen%2Fsupport%2Ftech-docs%2Famd64-technology- > &data=05%7C0 > > > 1%7Cbabu.moger%40amd.com%7C50e1807651fd4513648908dacd7efac0%7C3 > dd8961f > > > e4884e608e11a82d994e183d%7C0%7C0%7C638048242504277761%7CUnknow > n%7CTWFp > > > bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6 > Mn > > > 0%3D%7C3000%7C%7C%7C&sdata=5lpXbZkZ78mJ1d9PnLf7WmRT5vPogfs > 5HaZLz76 > > x04I%3D&reserved=0 > > platform-quality-service-extensions > > Link: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > > > illa.kernel.org%2Fshow_bug.cgi%3Fid%3D206537&data=05%7C01%7Cbab > u.m > > > oger%40amd.com%7C50e1807651fd4513648908dacd7efac0%7C3dd8961fe488 > 4e608e > > > 11a82d994e183d%7C0%7C0%7C638048242504277761%7CUnknown%7CTWFpb > GZsb3d8ey > > > JWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C300 > > > 0%7C%7C%7C&sdata=2CjPpzCT4JeA9VPNZIW7zxyL22xpEm2FoXQlhAz5OK > o%3D&am > > p;reserved=0 > > Signed-off-by: Babu Moger <babu.moger@amd.com> > > --- > > arch/x86/include/asm/cpufeatures.h | 1 + > > arch/x86/kernel/cpu/cpuid-deps.c | 1 + > > arch/x86/kernel/cpu/scattered.c | 1 + > > 3 files changed, 3 insertions(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h > > b/arch/x86/include/asm/cpufeatures.h > > index d68b4c9c181d..6732ca0117be 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -306,6 +306,7 @@ > > #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on > VM > > exit when EIBRS is enabled */ > > #define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth > > tracking for RSB stuffing */ > > #define X86_FEATURE_SMBA (11*32+19) /* Slow Memory > > Bandwidth Allocation */ > > +#define X86_FEATURE_BMEC (11*32+20) /* AMD > Bandwidth > > Monitoring Event Configuration (BMEC) */ > > > > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ > > #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI > > instructions */ > > diff --git a/arch/x86/kernel/cpu/cpuid-deps.c > > b/arch/x86/kernel/cpu/cpuid- deps.c index c881bcafba7d..4555f9596ccf > > 100644 > > --- a/arch/x86/kernel/cpu/cpuid-deps.c > > +++ b/arch/x86/kernel/cpu/cpuid-deps.c > > @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] = { > > { X86_FEATURE_CQM_OCCUP_LLC, > > X86_FEATURE_CQM_LLC }, > > { X86_FEATURE_CQM_MBM_TOTAL, > > X86_FEATURE_CQM_LLC }, > > { X86_FEATURE_CQM_MBM_LOCAL, > > X86_FEATURE_CQM_LLC }, > > + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC }, > > Shouldn't X86_FEATURE_BMEC really depend on > X86_FEATURE_CQM_MBM_LOCAL and _TOTAL? > > CQM_MBM_LOCAL and/or _TOTAL can be disabled but CQM_LLC can still be > enabled. In this case, BMEC shouldn't be enabled, right? But with this patch, > BMEC will be enabled but it won't work well as CQM_MBM_TOTAL/_LOCAL > are not enabled. Yes. You are right. > > You may remove the above line and add these two lines: > > + { X86_FEATURE_BMEC, > X86_FEATURE_CQM_MBM_TOTAL }, > + { X86_FEATURE_BMEC, > X86_FEATURE_CQM_MBM_LOCAL }, > Sure. Will add these lines. Thanks Babu
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d68b4c9c181d..6732ca0117be 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -306,6 +306,7 @@ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ #define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth tracking for RSB stuffing */ #define X86_FEATURE_SMBA (11*32+19) /* Slow Memory Bandwidth Allocation */ +#define X86_FEATURE_BMEC (11*32+20) /* AMD Bandwidth Monitoring Event Configuration (BMEC) */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index c881bcafba7d..4555f9596ccf 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 5a5f17ed69a2..67c4d24e06ef 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 }