Message ID | 20221122155324.1878416-2-ira.weiny@intel.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2293290wrr; Tue, 22 Nov 2022 08:00:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf6FfGn+5Y2Gnm9ApZkLyloF512ocO4Ip3IE2MwIu9PFaOqrnngvj1xCYyCySkIgQCIcTzsn X-Received: by 2002:a63:1054:0:b0:42b:9219:d14e with SMTP id 20-20020a631054000000b0042b9219d14emr4746923pgq.176.1669132838106; Tue, 22 Nov 2022 08:00:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669132838; cv=none; d=google.com; s=arc-20160816; b=JRnimxCZa8sVyScVVXoG6muV2j9Q3rHfjSGVj7iLRde49RRJo/KAYTbGePEeuJ+ZMS ce09Pzz5JekCsZ7/35LazCCKrW7W34ogKj1QpItfANLYMXjUJ07cIXcfKo8fF44AiFsS hoFLVZ/OneerFhGJaMOdZAfD4pvCLkjIPzzTC9Y6cxz8Ca7HJR+E6MWJIPOyEMfscgb6 BUDIDlzmJpKCjhrt4pizhD/FLILgXRswerY5xk+wFk21kd9hlS54suSIeAMuXYsg3A2r dvXqyt9Fovgkq6RYhm2b6KVXakCbxl0X7s2KQTChTfEko3d1jaGehQc3hWIEBADw+g13 tKpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=agyc7s6h16IO6Q24kCBwX6rl76erMQSODes1pYlgfmg=; b=ZdHokyRfO1KoRdBdEThibkx7+X3LxXV8aTVfTC8XKbc1aYMmJmj53C/EqcNmAu9AkJ EoBBHPbyxYNxFZNTqXAJTu0Wek3BfjaepIpJpFIYtAbirgXGOGZQi50dRKZ+8hwrBAGT KQxvG10u98ZeVsjLh/oq31yZSSQoJ7HvS0wFbaaLfPomUl38d3XRX4/GBwdUitB0uMt9 pLIIvMQMw/Fk5VkOeYr89F6PX7hy5SSoKDnEYI1ckdsbp0uOVOZqvp7nTc/+CJWcQqyn ICs19yZHV3VjCeuor6hTsvvL8opwwqozcUJ5yeKxahBolAAt7wkv+Nhku9FeaKTRMm5O JFSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kvgOBGhV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 2-20020a630b02000000b004498b9c8d34si14954423pgl.682.2022.11.22.08.00.23; Tue, 22 Nov 2022 08:00:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kvgOBGhV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233942AbiKVPxd (ORCPT <rfc822;cjcooper78@gmail.com> + 99 others); Tue, 22 Nov 2022 10:53:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233626AbiKVPx3 (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 22 Nov 2022 10:53:29 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BB3E48779; Tue, 22 Nov 2022 07:53:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669132408; x=1700668408; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YUJ7EdYfUOaMRwptVpLuSUm6x5AoT6ZUjcLdR6MstiY=; b=kvgOBGhVXFJVFRcBO54KKqM/RGEUdFFFFxBpezx7FOXgnyg0ew0q/Qp9 2sV586QTDlHRV9xxYAgBIcnMWV5hAI3B1O+Y9wWzADOJzQTgnNhHDyA/u 3lZNVZYDN9bhsI5u31pP64xXb82ypEgm/C+n/hwE9IJBtUv3uy1lYaDVy axBlJkSjNqoBGXFQ0HERl10eSrBlxhe+SYba8hmnUpf5XCEnuhKE1QBWd fm+QnllWbcCIoJjgIz1GUJJ8aMZdiVm3VzYj1P3hCRSQaxWVljYVJqpHm TczU7eBHyCAseqmM0kEamdoyUD4srK8omwMstoGgvIk+nrZetiqzf9jrx Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="313877730" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="313877730" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 07:53:28 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="816142053" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="816142053" Received: from iweiny-mobl.amr.corp.intel.com (HELO localhost) ([10.209.130.75]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 07:53:27 -0800 From: ira.weiny@intel.com To: Dan Williams <dan.j.williams@intel.com>, Bjorn Helgaas <bhelgaas@google.com> Cc: Ira Weiny <ira.weiny@intel.com>, Lukas Wunner <lukas@wunner.de>, Alison Schofield <alison.schofield@intel.com>, Vishal Verma <vishal.l.verma@intel.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Gregory Price <gregory.price@memverge.com>, "Li, Ming" <ming4.li@intel.com>, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [PATCH V2 1/2] PCI/DOE: Remove the pci_doe_flush_mb() call Date: Tue, 22 Nov 2022 07:53:23 -0800 Message-Id: <20221122155324.1878416-2-ira.weiny@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221122155324.1878416-1-ira.weiny@intel.com> References: <20221122155324.1878416-1-ira.weiny@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750212634766756725?= X-GMAIL-MSGID: =?utf-8?q?1750212634766756725?= |
Series |
PCI/DOE: Remove asynchronous task support
|
|
Commit Message
Ira Weiny
Nov. 22, 2022, 3:53 p.m. UTC
From: Ira Weiny <ira.weiny@intel.com> Each struct doe_mb is managed as part of the PCI device. They can't go away as long as the PCI device exists. pci_doe_flush_mb() was set up to flush the workqueue and prevent any further submissions to the mailboxes when the PCI device goes away. Unfortunately, this was fundamentally flawed. There was no guarantee that a struct doe_mb remained after pci_doe_flush_mb() returned. Therefore, the doe_mb state could be invalid when those threads waiting on the workqueue were flushed. Fortunately the current code is safe because all callers make a synchronous call to pci_doe_submit_task() and maintain a reference on the PCI device. For these reasons, pci_doe_flush_mb() will never be called while tasks are being processed and there is no use for it. Remove the dead code around pci_doe_flush_mb(). Signed-off-by: Ira Weiny <ira.weiny@intel.com> --- drivers/pci/doe.c | 48 ++++------------------------------------------- 1 file changed, 4 insertions(+), 44 deletions(-)
Comments
On Tue, 22 Nov 2022 07:53:23 -0800 ira.weiny@intel.com wrote: > From: Ira Weiny <ira.weiny@intel.com> > > Each struct doe_mb is managed as part of the PCI device. They can't go > away as long as the PCI device exists. pci_doe_flush_mb() was set up to > flush the workqueue and prevent any further submissions to the mailboxes > when the PCI device goes away. Unfortunately, this was fundamentally > flawed. There was no guarantee that a struct doe_mb remained after > pci_doe_flush_mb() returned. Therefore, the doe_mb state could be > invalid when those threads waiting on the workqueue were flushed. > > Fortunately the current code is safe because all callers make a > synchronous call to pci_doe_submit_task() and maintain a reference on the > PCI device. > > For these reasons, pci_doe_flush_mb() will never be called while tasks > are being processed and there is no use for it. > > Remove the dead code around pci_doe_flush_mb(). > > Signed-off-by: Ira Weiny <ira.weiny@intel.com> Looks fine I think, though one question inline. > --- > drivers/pci/doe.c | 48 ++++------------------------------------------- > 1 file changed, 4 insertions(+), 44 deletions(-) > > diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c > index e402f05068a5..260313e9052e 100644 > --- a/drivers/pci/doe.c > +++ b/drivers/pci/doe.c > @@ -24,10 +24,9 @@ > > /* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */ > #define PCI_DOE_TIMEOUT HZ > -#define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128) > +#define PCI_DOE_POLL_INTERVAL 8 Why this change? > > -#define PCI_DOE_FLAG_CANCEL 0 > -#define PCI_DOE_FLAG_DEAD 1 > +#define PCI_DOE_FLAG_DEAD 0 > > /** > * struct pci_doe_mb - State for a single DOE mailbox > @@ -53,15 +52,6 @@ struct pci_doe_mb { > unsigned long flags; > }; > > -static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout) > -{ > - if (wait_event_timeout(doe_mb->wq, > - test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags), > - timeout)) > - return -EIO; > - return 0; > -} > - > static void pci_doe_write_ctrl(struct pci_doe_mb *doe_mb, u32 val) > { > struct pci_dev *pdev = doe_mb->pdev; > @@ -82,12 +72,9 @@ static int pci_doe_abort(struct pci_doe_mb *doe_mb) > pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_ABORT); > > do { > - int rc; > u32 val; > > - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); > - if (rc) > - return rc; > + msleep_interruptible(PCI_DOE_POLL_INTERVAL); > pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); > > /* Abort success! */ > @@ -278,11 +265,7 @@ static void doe_statemachine_work(struct work_struct *work) > signal_task_abort(task, -EIO); > return; > } > - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); > - if (rc) { > - signal_task_abort(task, rc); > - return; > - } > + msleep_interruptible(PCI_DOE_POLL_INTERVAL); > goto retry_resp; > } > > @@ -383,21 +366,6 @@ static void pci_doe_destroy_workqueue(void *mb) > destroy_workqueue(doe_mb->work_queue); > } > > -static void pci_doe_flush_mb(void *mb) > -{ > - struct pci_doe_mb *doe_mb = mb; > - > - /* Stop all pending work items from starting */ > - set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags); > - > - /* Cancel an in progress work item, if necessary */ > - set_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags); > - wake_up(&doe_mb->wq); > - > - /* Flush all work items */ > - flush_workqueue(doe_mb->work_queue); > -} > - > /** > * pcim_doe_create_mb() - Create a DOE mailbox object > * > @@ -450,14 +418,6 @@ struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset) > return ERR_PTR(rc); > } > > - /* > - * The state machine and the mailbox should be in sync now; > - * Set up mailbox flush prior to using the mailbox to query protocols. > - */ > - rc = devm_add_action_or_reset(dev, pci_doe_flush_mb, doe_mb); > - if (rc) > - return ERR_PTR(rc); > - > rc = pci_doe_cache_protocols(doe_mb); > if (rc) { > pci_err(pdev, "[%x] failed to cache protocols : %d\n",
On Tue, Nov 22, 2022 at 07:53:23AM -0800, ira.weiny@intel.com wrote: > Each struct doe_mb is managed as part of the PCI device. They can't go > away as long as the PCI device exists. pci_doe_flush_mb() was set up to > flush the workqueue and prevent any further submissions to the mailboxes > when the PCI device goes away. Unfortunately, this was fundamentally > flawed. There was no guarantee that a struct doe_mb remained after > pci_doe_flush_mb() returned. Therefore, the doe_mb state could be > invalid when those threads waiting on the workqueue were flushed. > > Fortunately the current code is safe because all callers make a > synchronous call to pci_doe_submit_task() and maintain a reference on the > PCI device. > > For these reasons, pci_doe_flush_mb() will never be called while tasks > are being processed and there is no use for it. Going forward my plan is to allocate all existing DOE mailboxes of a device upon enumeration. That will allow concurrent use of a mailbox by multiple drivers. When a pci_dev goes away, say, because it's been hot-removed, we need a way to abort all ongoing DOE exchanges. pci_doe_flush_mb() seems to do just that so I'm not sure why it's being removed? Thanks, Lukas
On Tue, Nov 22, 2022 at 04:34:26PM +0000, Jonathan Cameron wrote: > On Tue, 22 Nov 2022 07:53:23 -0800 > ira.weiny@intel.com wrote: > > > From: Ira Weiny <ira.weiny@intel.com> > > > > Each struct doe_mb is managed as part of the PCI device. They can't go > > away as long as the PCI device exists. pci_doe_flush_mb() was set up to > > flush the workqueue and prevent any further submissions to the mailboxes > > when the PCI device goes away. Unfortunately, this was fundamentally > > flawed. There was no guarantee that a struct doe_mb remained after > > pci_doe_flush_mb() returned. Therefore, the doe_mb state could be > > invalid when those threads waiting on the workqueue were flushed. > > > > Fortunately the current code is safe because all callers make a > > synchronous call to pci_doe_submit_task() and maintain a reference on the > > PCI device. > > > > For these reasons, pci_doe_flush_mb() will never be called while tasks > > are being processed and there is no use for it. > > > > Remove the dead code around pci_doe_flush_mb(). > > > > Signed-off-by: Ira Weiny <ira.weiny@intel.com> > > Looks fine I think, though one question inline. > > > --- > > drivers/pci/doe.c | 48 ++++------------------------------------------- > > 1 file changed, 4 insertions(+), 44 deletions(-) > > > > diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c > > index e402f05068a5..260313e9052e 100644 > > --- a/drivers/pci/doe.c > > +++ b/drivers/pci/doe.c > > @@ -24,10 +24,9 @@ > > > > /* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */ > > #define PCI_DOE_TIMEOUT HZ > > -#define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128) > > +#define PCI_DOE_POLL_INTERVAL 8 > > Why this change? msleep_interruptible() takes a millisecond value and wait_event_timeout() takes jiffies. 1/128 of a second is ~8ms. While for most configs (HZ == 1000) the value does not change. I don't believe this would be true for all configs. Thus a more explicit define. I'll add a comment. Ira > > > > > -#define PCI_DOE_FLAG_CANCEL 0 > > -#define PCI_DOE_FLAG_DEAD 1 > > +#define PCI_DOE_FLAG_DEAD 0 > > > > /** > > * struct pci_doe_mb - State for a single DOE mailbox > > @@ -53,15 +52,6 @@ struct pci_doe_mb { > > unsigned long flags; > > }; > > > > -static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout) > > -{ > > - if (wait_event_timeout(doe_mb->wq, > > - test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags), > > - timeout)) > > - return -EIO; > > - return 0; > > -} > > - > > static void pci_doe_write_ctrl(struct pci_doe_mb *doe_mb, u32 val) > > { > > struct pci_dev *pdev = doe_mb->pdev; > > @@ -82,12 +72,9 @@ static int pci_doe_abort(struct pci_doe_mb *doe_mb) > > pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_ABORT); > > > > do { > > - int rc; > > u32 val; > > > > - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); > > - if (rc) > > - return rc; > > + msleep_interruptible(PCI_DOE_POLL_INTERVAL); > > pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); > > > > /* Abort success! */ > > @@ -278,11 +265,7 @@ static void doe_statemachine_work(struct work_struct *work) > > signal_task_abort(task, -EIO); > > return; > > } > > - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); > > - if (rc) { > > - signal_task_abort(task, rc); > > - return; > > - } > > + msleep_interruptible(PCI_DOE_POLL_INTERVAL); > > goto retry_resp; > > } > > > > @@ -383,21 +366,6 @@ static void pci_doe_destroy_workqueue(void *mb) > > destroy_workqueue(doe_mb->work_queue); > > } > > > > -static void pci_doe_flush_mb(void *mb) > > -{ > > - struct pci_doe_mb *doe_mb = mb; > > - > > - /* Stop all pending work items from starting */ > > - set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags); > > - > > - /* Cancel an in progress work item, if necessary */ > > - set_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags); > > - wake_up(&doe_mb->wq); > > - > > - /* Flush all work items */ > > - flush_workqueue(doe_mb->work_queue); > > -} > > - > > /** > > * pcim_doe_create_mb() - Create a DOE mailbox object > > * > > @@ -450,14 +418,6 @@ struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset) > > return ERR_PTR(rc); > > } > > > > - /* > > - * The state machine and the mailbox should be in sync now; > > - * Set up mailbox flush prior to using the mailbox to query protocols. > > - */ > > - rc = devm_add_action_or_reset(dev, pci_doe_flush_mb, doe_mb); > > - if (rc) > > - return ERR_PTR(rc); > > - > > rc = pci_doe_cache_protocols(doe_mb); > > if (rc) { > > pci_err(pdev, "[%x] failed to cache protocols : %d\n", >
On Tue, Nov 22, 2022 at 08:53:16PM +0100, Lukas Wunner wrote: > On Tue, Nov 22, 2022 at 07:53:23AM -0800, ira.weiny@intel.com wrote: > > Each struct doe_mb is managed as part of the PCI device. They can't go > > away as long as the PCI device exists. pci_doe_flush_mb() was set up to > > flush the workqueue and prevent any further submissions to the mailboxes > > when the PCI device goes away. Unfortunately, this was fundamentally > > flawed. There was no guarantee that a struct doe_mb remained after > > pci_doe_flush_mb() returned. Therefore, the doe_mb state could be > > invalid when those threads waiting on the workqueue were flushed. > > > > Fortunately the current code is safe because all callers make a > > synchronous call to pci_doe_submit_task() and maintain a reference on the > > PCI device. > > > > For these reasons, pci_doe_flush_mb() will never be called while tasks > > are being processed and there is no use for it. > > Going forward my plan is to allocate all existing DOE mailboxes > of a device upon enumeration. That will allow concurrent use > of a mailbox by multiple drivers. > > When a pci_dev goes away, say, because it's been hot-removed, > we need a way to abort all ongoing DOE exchanges. > > pci_doe_flush_mb() seems to do just that so I'm not sure why > it's being removed? I guess I was not explicit enough in the commit message. 1) it is not used today. More importantly 2) it does not work. Because we are not using it currently I thought it best to remove it rather than try and fix it. Once we have a use then we can figure out how to make sure the doe_mb[*] is valid until all tasks are flushed. Ira [*] Probably with a reference on the struct as was discussed before. -- https://lore.kernel.org/all/20221122094627.00003f2c@Huawei.com/ > > Thanks, > > Lukas
On Wed, 23 Nov 2022 09:35:37 -0800 Ira Weiny <ira.weiny@intel.com> wrote: > On Tue, Nov 22, 2022 at 04:34:26PM +0000, Jonathan Cameron wrote: > > On Tue, 22 Nov 2022 07:53:23 -0800 > > ira.weiny@intel.com wrote: > > > > > From: Ira Weiny <ira.weiny@intel.com> > > > > > > Each struct doe_mb is managed as part of the PCI device. They can't go > > > away as long as the PCI device exists. pci_doe_flush_mb() was set up to > > > flush the workqueue and prevent any further submissions to the mailboxes > > > when the PCI device goes away. Unfortunately, this was fundamentally > > > flawed. There was no guarantee that a struct doe_mb remained after > > > pci_doe_flush_mb() returned. Therefore, the doe_mb state could be > > > invalid when those threads waiting on the workqueue were flushed. > > > > > > Fortunately the current code is safe because all callers make a > > > synchronous call to pci_doe_submit_task() and maintain a reference on the > > > PCI device. > > > > > > For these reasons, pci_doe_flush_mb() will never be called while tasks > > > are being processed and there is no use for it. > > > > > > Remove the dead code around pci_doe_flush_mb(). > > > > > > Signed-off-by: Ira Weiny <ira.weiny@intel.com> > > > > Looks fine I think, though one question inline. > > > > > --- > > > drivers/pci/doe.c | 48 ++++------------------------------------------- > > > 1 file changed, 4 insertions(+), 44 deletions(-) > > > > > > diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c > > > index e402f05068a5..260313e9052e 100644 > > > --- a/drivers/pci/doe.c > > > +++ b/drivers/pci/doe.c > > > @@ -24,10 +24,9 @@ > > > > > > /* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */ > > > #define PCI_DOE_TIMEOUT HZ > > > -#define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128) > > > +#define PCI_DOE_POLL_INTERVAL 8 > > > > Why this change? > > msleep_interruptible() takes a millisecond value and wait_event_timeout() takes > jiffies. 1/128 of a second is ~8ms. > > While for most configs (HZ == 1000) the value does not change. I don't believe > this would be true for all configs. Thus a more explicit define. > Makes sense. Maybe add a postfix as well to make it clear it's not in same units as the PCI_DOE_TIMEOUT? PCI_DOE_POLL_INTERVAL_MSECS > I'll add a comment. > > Ira > > > > > > > > > -#define PCI_DOE_FLAG_CANCEL 0 > > > -#define PCI_DOE_FLAG_DEAD 1 > > > +#define PCI_DOE_FLAG_DEAD 0 > > > > > > /** > > > * struct pci_doe_mb - State for a single DOE mailbox > > > @@ -53,15 +52,6 @@ struct pci_doe_mb { > > > unsigned long flags; > > > }; > > > > > > -static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout) > > > -{ > > > - if (wait_event_timeout(doe_mb->wq, > > > - test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags), > > > - timeout)) > > > - return -EIO; > > > - return 0; > > > -} > > > - > > > static void pci_doe_write_ctrl(struct pci_doe_mb *doe_mb, u32 val) > > > { > > > struct pci_dev *pdev = doe_mb->pdev; > > > @@ -82,12 +72,9 @@ static int pci_doe_abort(struct pci_doe_mb *doe_mb) > > > pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_ABORT); > > > > > > do { > > > - int rc; > > > u32 val; > > > > > > - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); > > > - if (rc) > > > - return rc; > > > + msleep_interruptible(PCI_DOE_POLL_INTERVAL); > > > pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); > > > > > > /* Abort success! */ > > > @@ -278,11 +265,7 @@ static void doe_statemachine_work(struct work_struct *work) > > > signal_task_abort(task, -EIO); > > > return; > > > } > > > - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); > > > - if (rc) { > > > - signal_task_abort(task, rc); > > > - return; > > > - } > > > + msleep_interruptible(PCI_DOE_POLL_INTERVAL); > > > goto retry_resp; > > > } > > > > > > @@ -383,21 +366,6 @@ static void pci_doe_destroy_workqueue(void *mb) > > > destroy_workqueue(doe_mb->work_queue); > > > } > > > > > > -static void pci_doe_flush_mb(void *mb) > > > -{ > > > - struct pci_doe_mb *doe_mb = mb; > > > - > > > - /* Stop all pending work items from starting */ > > > - set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags); > > > - > > > - /* Cancel an in progress work item, if necessary */ > > > - set_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags); > > > - wake_up(&doe_mb->wq); > > > - > > > - /* Flush all work items */ > > > - flush_workqueue(doe_mb->work_queue); > > > -} > > > - > > > /** > > > * pcim_doe_create_mb() - Create a DOE mailbox object > > > * > > > @@ -450,14 +418,6 @@ struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset) > > > return ERR_PTR(rc); > > > } > > > > > > - /* > > > - * The state machine and the mailbox should be in sync now; > > > - * Set up mailbox flush prior to using the mailbox to query protocols. > > > - */ > > > - rc = devm_add_action_or_reset(dev, pci_doe_flush_mb, doe_mb); > > > - if (rc) > > > - return ERR_PTR(rc); > > > - > > > rc = pci_doe_cache_protocols(doe_mb); > > > if (rc) { > > > pci_err(pdev, "[%x] failed to cache protocols : %d\n", > > >
diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c index e402f05068a5..260313e9052e 100644 --- a/drivers/pci/doe.c +++ b/drivers/pci/doe.c @@ -24,10 +24,9 @@ /* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */ #define PCI_DOE_TIMEOUT HZ -#define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128) +#define PCI_DOE_POLL_INTERVAL 8 -#define PCI_DOE_FLAG_CANCEL 0 -#define PCI_DOE_FLAG_DEAD 1 +#define PCI_DOE_FLAG_DEAD 0 /** * struct pci_doe_mb - State for a single DOE mailbox @@ -53,15 +52,6 @@ struct pci_doe_mb { unsigned long flags; }; -static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout) -{ - if (wait_event_timeout(doe_mb->wq, - test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags), - timeout)) - return -EIO; - return 0; -} - static void pci_doe_write_ctrl(struct pci_doe_mb *doe_mb, u32 val) { struct pci_dev *pdev = doe_mb->pdev; @@ -82,12 +72,9 @@ static int pci_doe_abort(struct pci_doe_mb *doe_mb) pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_ABORT); do { - int rc; u32 val; - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); - if (rc) - return rc; + msleep_interruptible(PCI_DOE_POLL_INTERVAL); pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); /* Abort success! */ @@ -278,11 +265,7 @@ static void doe_statemachine_work(struct work_struct *work) signal_task_abort(task, -EIO); return; } - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); - if (rc) { - signal_task_abort(task, rc); - return; - } + msleep_interruptible(PCI_DOE_POLL_INTERVAL); goto retry_resp; } @@ -383,21 +366,6 @@ static void pci_doe_destroy_workqueue(void *mb) destroy_workqueue(doe_mb->work_queue); } -static void pci_doe_flush_mb(void *mb) -{ - struct pci_doe_mb *doe_mb = mb; - - /* Stop all pending work items from starting */ - set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags); - - /* Cancel an in progress work item, if necessary */ - set_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags); - wake_up(&doe_mb->wq); - - /* Flush all work items */ - flush_workqueue(doe_mb->work_queue); -} - /** * pcim_doe_create_mb() - Create a DOE mailbox object * @@ -450,14 +418,6 @@ struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset) return ERR_PTR(rc); } - /* - * The state machine and the mailbox should be in sync now; - * Set up mailbox flush prior to using the mailbox to query protocols. - */ - rc = devm_add_action_or_reset(dev, pci_doe_flush_mb, doe_mb); - if (rc) - return ERR_PTR(rc); - rc = pci_doe_cache_protocols(doe_mb); if (rc) { pci_err(pdev, "[%x] failed to cache protocols : %d\n",